corgi_lcd.rar_Sharp

/* * LCD/Backlight Driver for Sharp Zaurus Handhelds (various models) */ #include <linux/module.h> #include <linux/kernel.h> #include <linux/init.h> #include <linux/delay.h> #include <linux/gpio.h> #include <linux/fb.h> #include <linux/lcd.h> #include <linux/spi/spi.h> #include <linux/spi/corgi_lcd.h> #include <linux/slab.h> #include <asm/mach/sharpsl_param.h> #define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL) /* Register Addresses */ #define RESCTL_ADRS 0x00 #define PHACTRL_ADRS 0x01 #define DUTYCTRL_ADRS 0x02 #define POWERREG0_ADRS 0x03 #define POWERREG1_ADRS 0x04 #define GPOR3_ADRS 0x05 #define PICTRL_ADRS 0x06 #define POLCTRL_ADRS 0x07 /* Register Bit Definitions */ #define RESCTL_QVGA 0x01 #define RESCTL_VGA 0x00 #define POWER1_VW_ON 0x01 /* VW Supply FET ON */ #define POWER1_GVSS_ON 0x02 /* GVSS(-8V) Power Supply ON */ #define POWER1_VDD_ON 0x04 /* VDD(8V),SVSS(-4V) Power Supply ON */ #define POWER1_VW_OFF 0x00 /* VW Supply FET OFF */ #define POWER1_GVSS_OFF 0x00 /* GVSS(-8V) Power Supply OFF */ #define POWER1_VDD_OFF 0x00 /* VDD(8V),SVSS(-4V) Power Supply OFF */ #define POWER0_COM_DCLK 0x01 /* COM Voltage DC Bias DAC Serial Data Clock */ #define POWER0_COM_DOUT 0x02 /* COM Voltage DC Bias DAC Serial Data Out */ #define POWER0_DAC_ON 0x04 /* DAC Power Supply ON */ #define POWER0_COM_ON 0x08 /* COM Power Supply ON */ #define POWER0_VCC5_ON 0x10 /* VCC5 Power Supply ON */ #define POWER0_DAC_OFF 0x00 /* DAC Power Supply OFF */ #define POWER0_COM_OFF 0x00 /* COM Power Supply OFF */ #define POWER0_VCC5_OFF 0x00 /* VCC5 Power Supply OFF */ #define PICTRL_INIT_STATE 0x01 #define PICTRL_INIOFF 0x02 #define PICTRL_POWER_DOWN 0x04 #define PICTRL_COM_SIGNAL_OFF 0x08 #define PICTRL_DAC_SIGNAL_OFF 0x10 #define POLCTRL_SYNC_POL_FALL 0x01 #define POLCTRL_EN_POL_FALL 0x02 #define POLCTRL_DATA_POL_FALL 0x04 #define POLCTRL_SYNC_ACT_H 0x08 #define POLCTRL_EN_ACT_L 0x10 #define POLCTRL_SYNC_POL_RISE 0x00 #define POLCTRL_EN_POL_RISE 0x00 #define POLCTRL_DATA_POL_RISE 0x00 #define POLCTRL_SYNC_ACT_L 0x00 #define POLCTRL_EN_ACT_H 0x00 #define PHACTRL_PHASE_MANUAL 0x01 #define DEFAULT_PHAD_QVGA (9) #define DEFAULT_COMADJ (125) struct corgi_lcd { struct spi_device *spi_dev; struct lcd_device *lcd_dev; struct backlight_device *bl_dev; int limit_mask; int intensity; int power; int mode; char buf[2]; int gpio_backlight_on; int gpio_backlight_cont; int gpio_backlight_cont_inverted; void (*kick_battery)(void); }; static int corgi_ssp_lcdtg_send(struct corgi_lcd *lcd, int reg, uint8_t val); static struct corgi_lcd *the_corgi_lcd; static unsigned long corgibl_flags; #define CORGIBL_SUSPENDED 0x01 #define CORGIBL_BATTLOW 0x02 /* * This is only a pseudo I2C interface. We can't use the standard kernel * routines as the interface is write only. We just assume the data is acked... */ static void lcdtg_ssp_i2c_send(struct corgi_lcd *lcd, uint8_t data) { corgi_ssp_lcdtg_send(lcd, POWERREG0_ADRS, data); udelay(10); } static void lcdtg_i2c_send_bit(struct corgi_lcd *lcd, uint8_t data) { lcdtg_ssp_i2c_send(lcd, data); lcdtg_ssp_i2c_send(lcd, data | POWER0_COM_DCLK); lcdtg_ssp_i2c_send(lcd, data); } static void lcdtg_i2c_send_start(struct corgi_lcd *lcd, uint8_t base) { lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK | POWER0_COM_DOUT); lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK); lcdtg_ssp_i2c_send(lcd, base); } static void lcdtg_i2c_send_stop(struct corgi_lcd *lcd, uint8_t base) { lcdtg_ssp_i2c_send(lcd, base); lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK); lcdtg_ssp_i2c_send(lcd, base | POWER0_COM_DCLK | POWER0_COM_DOUT); } static void lcdtg_i2c_send_byte(struct corgi_lcd *lcd, uint8_t base, uint8_t data) { int i; for (i = 0; i < 8; i++) { if (data & 0x80) lcdtg_i2c_send_bit(lcd, base | POWER0_COM_DOUT); else lcdtg_i2c_send_bit(lcd, base); data <<= 1; } } static void lcdtg_i2c_wait_ack(struct corgi_lcd *lcd, uint8_t base) { lcdtg_i2c_send_bit(lcd, base); } static void lcdtg_set_common_voltage(struct corgi_lcd *lcd, uint8_t base_data, uint8_t data) { /* Set Common Voltage to M62332FP via I2C */ lcdtg_i2c_send_start(lcd, base_data); lcdtg_i2c_send_byte(lcd, base_data, 0x9c); lcdtg_i2c_wait_ack(lcd, base_data); lcdtg_i2c_send_byte(lcd, base_data, 0x00); lcdtg_i2c_wait_ack(lcd, base_data); lcdtg_i2c_send_byte(lcd, base_data, data); lcdtg_i2c_wait_ack(lcd, base_data); lcdtg_i2c_send_stop(lcd, base_data); } static int corgi_ssp_lcdtg_send(struct corgi_lcd *lcd, int adrs, uint8_t data) { struct spi_message msg; struct spi_transfer xfer = { .len = 1, .cs_change = 1, .tx_buf = lcd->buf, }; lcd->buf[0] = ((adrs & 0x07) << 5) | (data & 0x1f); spi_message_init(&msg); spi_message_add_tail(&xfer, &msg); return spi_sync(lcd->spi_dev, &msg); } /* Set Phase Adjust */ static void lcdtg_set_phadadj(struct corgi_lcd *lcd, int mode) { int adj; switch (mode) { case CORGI_LCD_MODE_VGA: /* Setting for VGA */ adj = sharpsl_param.phadadj; adj = (adj < 0) ? PHACTRL_PHASE_MANUAL : PHACTRL_PHASE_MANUAL | ((adj & 0xf) << 1); break; case CORGI_LCD_MODE_QVGA: default: /* Setting for QVGA */ adj = (DEFAULT_PHAD_QVGA << 1) | PHACTRL_PHASE_MANUAL; break; } corgi_ssp_lcdtg_send(lcd, PHACTRL_ADRS, adj); } static void corgi_lcd_power_on(struct corgi_lcd *lcd) { int comadj; /* Initialize Internal Logic & Port */ corgi_ssp_lcdtg_send(lcd, PICTRL_ADRS, PICTRL_POWER_DOWN | PICTRL_INIOFF | PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF | PICTRL_DAC_SIGNAL_OFF); corgi_ssp_lcdtg_send(lcd, POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_OFF | POWER0_COM_OFF | POWER0_VCC5_OFF); corgi_ssp_lcdtg_send(lcd, POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_OFF); /* VDD(+8V), SVSS(-4V) ON */ corgi_ssp_lcdtg_send(lcd, POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_OFF | POWER1_VDD_ON); mdelay(3); /* DAC ON */ corgi_ssp_lcdtg_send(lcd, POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF); /* INIB = H, INI = L */ /* PICTL[0] = H , PICTL[1] = PICTL[2] = PICTL[4] = L */ corgi_ssp_lcdtg_send(lcd, PICTRL_ADRS, PICTRL_INIT_STATE | PICTRL_COM_SIGNAL_OFF); /* Set Common Voltage */ comadj = sharpsl_param.comadj; if (comadj < 0) comadj = DEFAULT_COMADJ; lcdtg_set_common_voltage(lcd, POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_OFF, comadj); /* VCC5 ON, DAC ON */ corgi_ssp_lcdtg_send(lcd, POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON | POWER0_COM_OFF | POWER0_VCC5_ON); /* GVSS(-8V) ON, VDD ON */ corgi_ssp_lcdtg_send(lcd, POWERREG1_ADRS, POWER1_VW_OFF | POWER1_GVSS_ON | POWER1_VDD_ON); mdelay(2); /* COM SIGNAL ON (PICTL[3] = L) */ corgi_ssp_lcdtg_send(lcd, PICTRL_ADRS, PICTRL_INIT_STATE); /* COM ON, DAC ON, VCC5_ON */ corgi_ssp_lcdtg_send(lcd, POWERREG0_ADRS, POWER0_COM_DCLK | POWER0_COM_DOUT | POWER0_DAC_ON | POWER0_COM_ON | POWER0_VCC5_ON); /* VW ON, GVSS ON, VDD ON */ corgi_ssp_lcdtg_send(lcd, POWERREG1_ADRS, POWER1_VW_ON | POWER1_GVSS_ON | POWER1_VDD_ON); /* Signals output enable */ corgi_ssp_lcdtg_send(lcd, PICTRL_ADRS, 0); /* Set Phase Adjust */ lcdtg_set_phadadj(lcd, lcd->mode); /* Initialize for Input Signals from ATI */ corgi_ssp_lcdtg_send(lcd, POLCTRL_ADRS, POLCTRL_SYNC_POL_RISE | POLCTRL_EN_POL_RISE | POLCTRL_DATA_POL_RISE | POLCTRL_SYNC_ACT_L | POLCTRL_EN_ACT_H); udelay(1000); switch (lcd->mode) { case CORGI_LCD_MODE_VGA: corgi_ssp_lcdtg_send(lcd, RESCTL_ADRS, RESCTL_VGA); break; case CORGI_LCD_MODE_QVGA: default: corgi_ssp_lcdtg_send(lcd, RESCTL_ADRS, RESCTL_QVGA); break; } } static void corgi_lcd_power_off(struct corgi_lcd *lcd) { /* 60Hz x 2 frame = 16.7msec x 2 = 33.4 msec */ msleep(34); /* (1)VW OFF */ corgi_ssp_lcdtg_send(lcd, PO