/*******************************************************************************
*
* Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
* Copyright(c) 2013 - 2014 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along
* with this program. If not, see <http://www.gnu.org/licenses/>.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Contact Information:
* e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*
******************************************************************************/
#ifndef _I40E_TYPE_H_
#define _I40E_TYPE_H_
#include "i40e_status.h"
#include "i40e_osdep.h"
#include "i40e_register.h"
#include "i40e_adminq.h"
#include "i40e_hmc.h"
#include "i40e_lan_hmc.h"
/* Device IDs */
#define I40E_DEV_ID_SFP_XL710 0x1572
#define I40E_DEV_ID_QEMU 0x1574
#define I40E_DEV_ID_KX_A 0x157F
#define I40E_DEV_ID_KX_B 0x1580
#define I40E_DEV_ID_KX_C 0x1581
#define I40E_DEV_ID_QSFP_A 0x1583
#define I40E_DEV_ID_QSFP_B 0x1584
#define I40E_DEV_ID_QSFP_C 0x1585
#define I40E_DEV_ID_10G_BASE_T 0x1586
#define I40E_DEV_ID_VF 0x154C
#define I40E_DEV_ID_VF_HV 0x1571
#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
(d) == I40E_DEV_ID_QSFP_B || \
(d) == I40E_DEV_ID_QSFP_C)
/* I40E_MASK is a macro used on 32 bit registers */
#define I40E_MASK(mask, shift) (mask << shift)
#define I40E_MAX_VSI_QP 16
#define I40E_MAX_VF_VSI 3
#define I40E_MAX_CHAINED_RX_BUFFERS 5
#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
/* Max default timeout in ms, */
#define I40E_MAX_NVM_TIMEOUT 18000
/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
#define I40E_MS_TO_GTIME(time) ((time) * 1000)
/* forward declaration */
struct i40e_hw;
typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
/* Data type manipulation macros. */
#define I40E_DESC_UNUSED(R) \
((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
(R)->next_to_clean - (R)->next_to_use - 1)
/* bitfields for Tx queue mapping in QTX_CTL */
#define I40E_QTX_CTL_VF_QUEUE 0x0
#define I40E_QTX_CTL_VM_QUEUE 0x1
#define I40E_QTX_CTL_PF_QUEUE 0x2
/* debug masks - set these bits in hw->debug_mask to control output */
enum i40e_debug_mask {
I40E_DEBUG_INIT = 0x00000001,
I40E_DEBUG_RELEASE = 0x00000002,
I40E_DEBUG_LINK = 0x00000010,
I40E_DEBUG_PHY = 0x00000020,
I40E_DEBUG_HMC = 0x00000040,
I40E_DEBUG_NVM = 0x00000080,
I40E_DEBUG_LAN = 0x00000100,
I40E_DEBUG_FLOW = 0x00000200,
I40E_DEBUG_DCB = 0x00000400,
I40E_DEBUG_DIAG = 0x00000800,
I40E_DEBUG_FD = 0x00001000,
I40E_DEBUG_AQ_MESSAGE = 0x01000000,
I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
I40E_DEBUG_AQ_COMMAND = 0x06000000,
I40E_DEBUG_AQ = 0x0F000000,
I40E_DEBUG_USER = 0xF0000000,
I40E_DEBUG_ALL = 0xFFFFFFFF
};
/* These are structs for managing the hardware information and the operations.
* The structures of function pointers are filled out at init time when we
* know for sure exactly which hardware we're working with. This gives us the
* flexibility of using the same main driver code but adapting to slightly
* different hardware needs as new parts are developed. For this architecture,
* the Firmware and AdminQ are intended to insulate the driver from most of the
* future changes, but these structures will also do part of the job.
*/
enum i40e_mac_type {
I40E_MAC_UNKNOWN = 0,
I40E_MAC_X710,
I40E_MAC_XL710,
I40E_MAC_VF,
I40E_MAC_GENERIC,
};
enum i40e_media_type {
I40E_MEDIA_TYPE_UNKNOWN = 0,
I40E_MEDIA_TYPE_FIBER,
I40E_MEDIA_TYPE_BASET,
I40E_MEDIA_TYPE_BACKPLANE,
I40E_MEDIA_TYPE_CX4,
I40E_MEDIA_TYPE_DA,
I40E_MEDIA_TYPE_VIRTUAL
};
enum i40e_fc_mode {
I40E_FC_NONE = 0,
I40E_FC_RX_PAUSE,
I40E_FC_TX_PAUSE,
I40E_FC_FULL,
I40E_FC_PFC,
I40E_FC_DEFAULT
};
enum i40e_set_fc_aq_failures {
I40E_SET_FC_AQ_FAIL_NONE = 0,
I40E_SET_FC_AQ_FAIL_GET = 1,
I40E_SET_FC_AQ_FAIL_SET = 2,
I40E_SET_FC_AQ_FAIL_UPDATE = 4,
I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
};
enum i40e_vsi_type {
I40E_VSI_MAIN = 0,
I40E_VSI_VMDQ1,
I40E_VSI_VMDQ2,
I40E_VSI_CTRL,
I40E_VSI_FCOE,
I40E_VSI_MIRROR,
I40E_VSI_SRIOV,
I40E_VSI_FDIR,
I40E_VSI_TYPE_UNKNOWN
};
enum i40e_queue_type {
I40E_QUEUE_TYPE_RX = 0,
I40E_QUEUE_TYPE_TX,
I40E_QUEUE_TYPE_PE_CEQ,
I40E_QUEUE_TYPE_UNKNOWN
};
struct i40e_link_status {
enum i40e_aq_phy_type phy_type;
enum i40e_aq_link_speed link_speed;
u8 link_info;
u8 an_info;
u8 ext_info;
u8 loopback;
bool an_enabled;
/* is Link Status Event notification to SW enabled */
bool lse_enable;
u16 max_frame_size;
bool crc_enable;
u8 pacing;
};
struct i40e_phy_info {
struct i40e_link_status link_info;
struct i40e_link_status link_info_old;
u32 autoneg_advertised;
u32 phy_id;
u32 module_type;
bool get_link_info;
enum i40e_media_type media_type;
};
#define I40E_HW_CAP_MAX_GPIO 30
/* Capabilities of a PF or a VF or the whole device */
struct i40e_hw_capabilities {
u32 switch_mode;
#define I40E_NVM_IMAGE_TYPE_EVB 0x0
#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
u32 management_mode;
u32 npar_enable;
u32 os2bmc;
u32 valid_functions;
bool sr_iov_1_1;
bool vmdq;
bool evb_802_1_qbg; /* Edge Virtual Bridging */
bool evb_802_1_qbh; /* Bridge Port Extension */
bool dcb;
bool fcoe;
bool mfp_mode_1;
bool mgmt_cem;
bool ieee_1588;
bool iwarp;
bool fd;
u32 fd_filters_guaranteed;
u32 fd_filters_best_effort;
bool rss;
u32 rss_table_size;
u32 rss_table_entry_width;
bool led[I40E_HW_CAP_MAX_GPIO];
bool sdp[I40E_HW_CAP_MAX_GPIO];
u32 nvm_image_type;
u32 num_flow_director_filters;
u32 num_vfs;
u32 vf_base_id;
u32 num_vsis;
u32 num_rx_qp;
u32 num_tx_qp;
u32 base_queue;
u32 num_msix_vectors;
u32 num_msix_vectors_vf;
u32 led_pin_num;
u32 sdp_pin_num;
u32 mdio_port_num;
u32 mdio_port_mode;
u8 rx_buf_chain_len;
u32 enabled_tcmap;
u32 maxtc;
};
struct i40e_mac_info {
enum i40e_mac_type type;
u8 addr[ETH_ALEN];
u8 perm_addr[ETH_ALEN];
u8 san_addr[ETH_ALEN];
u16 max_fcoeq;
};
enum i40e_aq_resources_ids {
I40E_NVM_RESOURCE_ID = 1
};
enum i40e_aq_resource_access_type {
I40E_RESOURCE_READ = 1,
I40E_RESOURCE_WRITE
};
struct i40e_nvm_info {
u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
u32 timeout; /* [ms] */
u16 sr_size; /* Shadow RAM size in words */
bool blank_nvm_mode; /* is NVM empty (no FW present)*/
u16 version; /* NVM package version */
u32 eetrack; /* NVM data version */
};
/* definitions used in NVM update support */
enum i40e_nvmupd_cmd {
I40E_NVMUPD_INVALID,
I40E_NVMUPD_READ_CON,
I40E_NVMUPD_READ_SNT,
I40E_NVMUPD_READ_LCB,
I40E_NVMUPD_READ_SA,
I40E_NVMUPD_WRITE_ERA,
I40E_NVMUPD_WRITE_CON,
I40E_NVMUPD_WRITE_SNT,
I40E_NVMUPD_WRITE_LCB,
I40E_NVMUPD_WRITE_SA,
I40E_NVMUPD_CSUM_CON,
I40E_NVMUPD_CSUM_SA,
I40E_NVMUPD_CSUM_LCB,
};
enum i40e_nvmupd_state {
I40E_NVMUPD_STATE_INIT,
I40E_NVMUPD_STATE_READING,
I40E_NVMUPD_STATE_WRITING
};
/* nvm_access definition and its masks/shifts need to be accessible to
* application, core driver, and shared code. Where is the right file?
*/
#define I40E_NVM_READ 0xB
#define I40E_NVM_WRITE 0xC
#define I40E_NVM_MOD_PNT_MASK 0xFF
#define I40E_NVM_TRANS_SHIFT 8
#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHI