/******************************************************************************
FILE : datapage.c
PURPOSE : paged data access runtime routines
MACHINE : Freescale 68HC12 (Target)
LANGUAGE : ANSI-C
HISTORY : 21.7.96 first version created
******************************************************************************/
#include "hidef.h"
#include "non_bank.sgm"
#include "runtime.sgm"
/*lint --e{957} , MISRA 8.1 REQ, these are runtime support functions and, as such, are not meant to be called in user code; they are only invoked via jumps, in compiler-generated code */
/*lint -estring(553, __OPTION_ACTIVE__) , MISRA 19.11 REQ , __OPTION_ACTIVE__ is a built-in compiler construct to check for active compiler options */
#ifndef __HCS12X__ /* it's different for the HCS12X. See the text below at the #else // __HCS12X__ */
/*
According to the -Cp option of the compiler the
__DPAGE__, __PPAGE__ and __EPAGE__ macros are defined.
If none of them is given as argument, then no page accesses should occur and
this runtime routine should not be used !
To be on the save side, the runtime routines are created anyway.
*/
/* Compile with option -DHCS12 to activate this code */
#if defined(HCS12) || defined(_HCS12) || defined(__HCS12__)
#ifndef PPAGE_ADDR
#ifdef __PPAGE_ADR__
#define PPAGE_ADDR __PPAGE_ADR__
#else
#define PPAGE_ADDR (0x30 + REGISTER_BASE)
#endif
#endif
#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
#define __PPAGE__
#endif
/* Compile with option -DDG128 to activate this code */
#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */
#ifndef PPAGE_ADDR
#define PPAGE_ADDR (0xFF+REGISTER_BASE)
#endif
#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
#define __PPAGE__
#endif
#elif defined(HC812A4)
/* all setting default to A4 already */
#endif
#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__)
/* as default use all page registers */
#define __DPAGE__
#define __EPAGE__
#define __PPAGE__
#endif
/* modify the following defines to your memory configuration */
#define EPAGE_LOW_BOUND 0x400u
#define EPAGE_HIGH_BOUND 0x7ffu
#define DPAGE_LOW_BOUND 0x7000u
#define DPAGE_HIGH_BOUND 0x7fffu
#define PPAGE_LOW_BOUND (DPAGE_HIGH_BOUND+1u)
#define PPAGE_HIGH_BOUND 0xBFFFu
#ifndef REGISTER_BASE
#define REGISTER_BASE 0x0u
#endif
#ifndef DPAGE_ADDR
#define DPAGE_ADDR (0x34u+REGISTER_BASE)
#endif
#ifndef EPAGE_ADDR
#define EPAGE_ADDR (0x36u+REGISTER_BASE)
#endif
#ifndef PPAGE_ADDR
#define PPAGE_ADDR (0x35u+REGISTER_BASE)
#endif
/*
The following parts about the defines are assumed in the code of _GET_PAGE_REG :
- the memory region controlled by DPAGE is above the area controlled by the EPAGE and
below the area controlled by the PPAGE.
- the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1
*/
#if (EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND) || (EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND) || (DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND) || (DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND) || (PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND)
#error /* please adapt _GET_PAGE_REG for this non default page configuration */
#endif
#if (DPAGE_HIGH_BOUND+1u) != PPAGE_LOW_BOUND
#error /* please adapt _GET_PAGE_REG for this non default page configuration */
#endif
/* this module does either control if any access is in the bounds of the specified page or */
/* ,if only one page is specified, just use this page. */
/* This behavior is controlled by the define USE_SEVERAL_PAGES. */
/* If !USE_SEVERAL_PAGES does increase the performance significantly */
/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */
/* by this single page. But this is should not cause problems because the page is restored to the old value before any other access could occur */
#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__)
/* no page at all is specified */
/* only specifying the right pages will speed up these functions a lot */
#define USE_SEVERAL_PAGES 1
#elif (defined(__DPAGE__) && defined(__EPAGE__)) || (defined(__DPAGE__) && defined(__PPAGE__)) || (defined(__EPAGE__) && defined(__PPAGE__))
/* more than one page register is used */
#define USE_SEVERAL_PAGES 1
#else
#define USE_SEVERAL_PAGES 0
#if defined(__DPAGE__) /* check which pages are used */
#define PAGE_ADDR PPAGE_ADDR
#elif defined(__EPAGE__)
#define PAGE_ADDR EPAGE_ADDR
#elif defined(__PPAGE__)
#define PAGE_ADDR PPAGE_ADDR
#else /* we do not know which page, decide it at runtime */
#error /* must not happen */
#endif
#endif
#if USE_SEVERAL_PAGES /* only needed for several pages support */
/*--------------------------- _GET_PAGE_REG --------------------------------
Runtime routine to detect the right register depending on the 16 bit offset part
of an address.
This function is only used by the functions below.
Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced.
Arguments :
- Y : offset part of an address
Result :
if address Y is controlled by a page register :
- X : address of page register if Y is controlled by an page register
- Zero flag cleared
- all other registers remain unchanged
if address Y is not controlled by a page register :
- Zero flag is set
- all registers remain unchanged
--------------------------- _GET_PAGE_REG ----------------------------------*/
#if defined(__DPAGE__)
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
asm {
L_DPAGE:
CPY #DPAGE_LOW_BOUND ;/* test of lower bound of DPAGE */
#if defined(__EPAGE__)
BLO L_EPAGE ;/* EPAGE accesses are possible */
#else
BLO L_NOPAGE ;/* no paged memory below accesses */
#endif
CPY #DPAGE_HIGH_BOUND ;/* test of higher bound DPAGE/lower bound PPAGE */
#if defined(__PPAGE__)
BHI L_PPAGE ;/* EPAGE accesses are possible */
#else
BHI L_NOPAGE ;/* no paged memory above accesses */
#endif
FOUND_DPAGE:
LDX #DPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#if defined(__PPAGE__)
L_PPAGE:
CPY #PPAGE_HIGH_BOUND ;/* test of higher bound of PPAGE */
BHI L_NOPAGE
FOUND_PPAGE:
LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#endif
#if defined(__EPAGE__)
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */
BLO L_NOPAGE
CPY #EPAGE_HIGH_BOUND ;/* test of higher bound of EPAGE */
BHI L_NOPAGE
FOUND_EPAGE:
LDX #EPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#endif
L_NOPAGE:
ORCC #0x04 ;/* sets zero flag */
RTS
}
}
#else /* !defined(__DPAGE__) */
#if defined( __PPAGE__ )
#ifdef __cplusplus
extern "C"
#endif
#pragma NO_ENTRY
#pragma NO_EXIT
#pragma NO_FRAME
static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
asm {
L_PPAGE:
CPY #PPAGE_LOW_BOUND ;/* test of lower bound of PPAGE */
#if defined( __EPAGE__ )
BLO L_EPAGE
#else
BLO L_NOPAGE ;/* no paged memory below */
#endif
CPY #PPAGE_HIGH_BOUND ;/* test of higher bound PPAGE */
BHI L_NOPAGE
FOUND_PPAGE:
LDX #PPAGE_ADDR ;/* load page register address and clear zero flag */
RTS
#if defined( __EPAGE__ )
L_EPAGE:
CPY #EPAGE_LOW_BOUND ;/* test of lower bound of EPAGE */
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ZhiLi.rar_xs128 PID_陀螺仪_陀螺仪 PID
共100个文件
cmd:26个
o:19个
c:17个
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XS128的智能车控制程序,包括陀螺仪,加速度计的融合,及其PID 的控制参数调整
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ZhiLi.rar_xs128 PID_陀螺仪_陀螺仪 PID (100个子文件)
Project.abs 284KB
burner.bbl 10KB
burner.bbl 10KB
datapage.c 68KB
datapage.c 68KB
OLED.c 48KB
math.c 34KB
Start12.c 23KB
Start12.c 23KB
main.c 14KB
D_Flash.c 6KB
IIC_L3G4200D.C 6KB
Key_Control.c 5KB
AngDeal.c 5KB
System.c 4KB
main.c 4KB
CeSuPID.c 3KB
SCI_Output.c 2KB
OLED_Display.c 1KB
AT24C16.c 163B
Abatron_BDI_Erase_unsecure_hcs12xe.cmd 1KB
TBDML_Erase_unsecure_hcs12xe.cmd 1KB
TBDML_Erase_unsecure_hcs12xe.cmd 1KB
Abatron_BDI_Vppon.cmd 78B
TBDML_Vppon.cmd 78B
TBDML_Vppon.cmd 78B
TBDML_Vppoff.cmd 77B
Abatron_BDI_Vppoff.cmd 77B
TBDML_Vppoff.cmd 77B
Abatron_BDI_Preload.cmd 60B
TBDML_Preload.cmd 60B
Abatron_BDI_Reset.cmd 60B
TBDML_Reset.cmd 60B
Full_Chip_Simulation_Reset.cmd 60B
Full_Chip_Simulation_Preload.cmd 60B
TBDML_Preload.cmd 60B
TBDML_Reset.cmd 60B
TBDML_Postload.cmd 59B
Full_Chip_Simulation_Postload.cmd 59B
Full_Chip_Simulation_SetCPU.cmd 59B
Abatron_BDI_Postload.cmd 59B
Full_Chip_Simulation_Startup.cmd 59B
Abatron_BDI_Startup.cmd 59B
TBDML_Startup.cmd 59B
TBDML_Postload.cmd 59B
TBDML_Startup.cmd 59B
Project.abs.glo 27KB
math.h 6KB
D_Flash.h 4KB
OLED.h 3KB
common.h 3KB
IIC_L3G4200D.h 1KB
CeSuPID.h 786B
AngDeal.h 748B
System.h 524B
Key_Control.h 417B
derivative.h 262B
derivative.h 262B
SCI_Output.h 217B
OLED_Display.h 128B
AT24C16.h 107B
C_Layout.hwl 855B
C_Layout.hwl 855B
TBDML.ini 3KB
Full_Chip_Simulation.ini 1KB
Abatron_BDI.ini 937B
TBDML.ini 897B
CeSu.c.o.lst 2KB
Project.map 160KB
Project.map 27KB
1.mcp 58KB
ZhiLi.mcp 58KB
Default.mem 161B
Default.mem 161B
MC9S12XS128.c.o 160KB
MC9S12XS128.c.o 160KB
math.c.o 80KB
OLED.c.o 47KB
main.c.o 46KB
System.c.o 24KB
AngDeal.c.o 19KB
Key_Control.c.o 17KB
D_Flash.c.o 17KB
IIC_L3G4200D.C.o 15KB
datapage.c.o 14KB
datapage.c.o 14KB
CeSuPID.c.o 12KB
main.c.o 11KB
OLED_Display.c.o 8KB
SCI_Output.c.o 8KB
SCI_Output.c.o 8KB
Start12.c.o 6KB
Start12.c.o 5KB
Project.prm 6KB
Project.prm 6KB
Project.abs.s19 26KB
CWSettingsWindows.stg 4KB
CWSettingsWindows.stg 4KB
TargetDataWindows.tdt 508KB
TargetDataWindows.tdt 479KB
共 100 条
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