pwm.rar_MSP430F169 PWM_msp430f169_pwm

//******************************************************************************* // MSP430x24x Demo - Timer_A, PWM TA1-2, Up Mode, 32kHz ACLK // // Description: This program generates two PWM outputs on P1.2,3 using // Timer_A configured for up mode. The value in CCR0, 512-1, defines the PWM // period and the values in CCR1 and CCR2 the PWM duty cycles. Using 32kHz // ACLK as TACLK, the timer period is ~ (512/32k) ~ 15.6ms with a 75% duty // cycle on P1.2 and 25% on P1.3. Normal operating mode is LPM3. // ACLK = TACLK = LFXT1 = 32768Hz, MCLK = default DCO ~1.045Mhz. // //* External watch crystal on XIN XOUT is required for ACLK *// // // MSP430F249 // ----------------- // /|\| XIN|- // | | | 32kHz // --|RST XOUT|- // | | // | P1.2/TA1|--> CCR1 - 75% PWM // | P1.3/TA2|--> CCR2 - 25% PWM // // B. Nisarga // Texas Instruments Inc. // September 2007 // Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.42A //****************************************************************************** #include <msp430x16x.h> void delay(int i) { int j,k; for(j = 1000;j > 0;j--) for(k = i;k > 0;k--); } void main(void) { //int i = 200; WDTCTL = WDTPW + WDTHOLD; // Stop WDT P5DIR |= 0xFF; P5OUT = 0x00; P4DIR = 0xff; // P1.2 and P1.3 output P4SEL = 0xff; // P1.2 and P1.3 TA1/2 otions TBCCR0 = 10000; // PWM Period TBCCTL1 = OUTMOD_7; // CCR1 reset/set TBCCR1 = 5000; // CCR1 PWM duty cycle TBCCTL2 = OUTMOD_7; // CCR2 reset/set TBCCR2 = 3825; // CCR2 PWM duty cycle BCSCTL1 = RSEL0 + RSEL1 + RSEL2; BCSCTL2 |= SELS; TBCTL = TBSSEL_2 + MC_1 + ID_3; // SMCLK, up mode,0 Frequency divide while(1) { LPM1; } }