/* Intel Ethernet Switch Host Interface Driver
* Copyright(c) 2013 - 2014 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* The full GNU General Public License is included in this distribution in
* the file called "COPYING".
*
* Contact Information:
* e1000-devel Mailing List <[email protected]>
* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
*/
#ifndef _FM10K_TYPE_H_
#define _FM10K_TYPE_H_
/* forward declaration */
struct fm10k_hw;
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/etherdevice.h>
#include "fm10k_mbx.h"
#define FM10K_DEV_ID_PF 0x15A4
#define FM10K_DEV_ID_VF 0x15A5
#define FM10K_MAX_QUEUES 256
#define FM10K_MAX_QUEUES_PF 128
#define FM10K_MAX_QUEUES_POOL 16
#define FM10K_48_BIT_MASK 0x0000FFFFFFFFFFFFull
#define FM10K_STAT_VALID 0x80000000
/* PCI Bus Info */
#define FM10K_PCIE_LINK_CAP 0x7C
#define FM10K_PCIE_LINK_STATUS 0x82
#define FM10K_PCIE_LINK_WIDTH 0x3F0
#define FM10K_PCIE_LINK_WIDTH_1 0x10
#define FM10K_PCIE_LINK_WIDTH_2 0x20
#define FM10K_PCIE_LINK_WIDTH_4 0x40
#define FM10K_PCIE_LINK_WIDTH_8 0x80
#define FM10K_PCIE_LINK_SPEED 0xF
#define FM10K_PCIE_LINK_SPEED_2500 0x1
#define FM10K_PCIE_LINK_SPEED_5000 0x2
#define FM10K_PCIE_LINK_SPEED_8000 0x3
/* PCIe payload size */
#define FM10K_PCIE_DEV_CAP 0x74
#define FM10K_PCIE_DEV_CAP_PAYLOAD 0x07
#define FM10K_PCIE_DEV_CAP_PAYLOAD_128 0x00
#define FM10K_PCIE_DEV_CAP_PAYLOAD_256 0x01
#define FM10K_PCIE_DEV_CAP_PAYLOAD_512 0x02
#define FM10K_PCIE_DEV_CTRL 0x78
#define FM10K_PCIE_DEV_CTRL_PAYLOAD 0xE0
#define FM10K_PCIE_DEV_CTRL_PAYLOAD_128 0x00
#define FM10K_PCIE_DEV_CTRL_PAYLOAD_256 0x20
#define FM10K_PCIE_DEV_CTRL_PAYLOAD_512 0x40
/* PCIe MSI-X Capability info */
#define FM10K_PCI_MSIX_MSG_CTRL 0xB2
#define FM10K_PCI_MSIX_MSG_CTRL_TBL_SZ_MASK 0x7FF
#define FM10K_MAX_MSIX_VECTORS 256
#define FM10K_MAX_VECTORS_PF 256
#define FM10K_MAX_VECTORS_POOL 32
/* PCIe SR-IOV Info */
#define FM10K_PCIE_SRIOV_CTRL 0x190
#define FM10K_PCIE_SRIOV_CTRL_VFARI 0x10
#define FM10K_ERR_PARAM -2
#define FM10K_ERR_REQUESTS_PENDING -4
#define FM10K_ERR_RESET_REQUESTED -5
#define FM10K_ERR_DMA_PENDING -6
#define FM10K_ERR_RESET_FAILED -7
#define FM10K_ERR_INVALID_MAC_ADDR -8
#define FM10K_ERR_INVALID_VALUE -9
#define FM10K_NOT_IMPLEMENTED 0x7FFFFFFF
/* Start of PF registers */
#define FM10K_CTRL 0x0000
#define FM10K_CTRL_BAR4_ALLOWED 0x00000004
#define FM10K_CTRL_EXT 0x0001
#define FM10K_GCR 0x0003
#define FM10K_GCR_EXT 0x0005
/* Interrupt control registers */
#define FM10K_EICR 0x0006
#define FM10K_EICR_FAULT_MASK 0x0000003F
#define FM10K_EICR_MAILBOX 0x00000040
#define FM10K_EICR_SWITCHREADY 0x00000080
#define FM10K_EICR_SWITCHNOTREADY 0x00000100
#define FM10K_EICR_SWITCHINTERRUPT 0x00000200
#define FM10K_EICR_VFLR 0x00000800
#define FM10K_EICR_MAXHOLDTIME 0x00001000
#define FM10K_EIMR 0x0007
#define FM10K_EIMR_PCA_FAULT 0x00000001
#define FM10K_EIMR_THI_FAULT 0x00000010
#define FM10K_EIMR_FUM_FAULT 0x00000400
#define FM10K_EIMR_MAILBOX 0x00001000
#define FM10K_EIMR_SWITCHREADY 0x00004000
#define FM10K_EIMR_SWITCHNOTREADY 0x00010000
#define FM10K_EIMR_SWITCHINTERRUPT 0x00040000
#define FM10K_EIMR_SRAMERROR 0x00100000
#define FM10K_EIMR_VFLR 0x00400000
#define FM10K_EIMR_MAXHOLDTIME 0x01000000
#define FM10K_EIMR_ALL 0x55555555
#define FM10K_EIMR_DISABLE(NAME) ((FM10K_EIMR_ ## NAME) << 0)
#define FM10K_EIMR_ENABLE(NAME) ((FM10K_EIMR_ ## NAME) << 1)
#define FM10K_FAULT_ADDR_LO 0x0
#define FM10K_FAULT_ADDR_HI 0x1
#define FM10K_FAULT_SPECINFO 0x2
#define FM10K_FAULT_FUNC 0x3
#define FM10K_FAULT_SIZE 0x4
#define FM10K_FAULT_FUNC_VALID 0x00008000
#define FM10K_FAULT_FUNC_PF 0x00004000
#define FM10K_FAULT_FUNC_VF_MASK 0x00003F00
#define FM10K_FAULT_FUNC_VF_SHIFT 8
#define FM10K_FAULT_FUNC_TYPE_MASK 0x000000FF
#define FM10K_PCA_FAULT 0x0008
#define FM10K_THI_FAULT 0x0010
#define FM10K_FUM_FAULT 0x001C
/* Rx queue timeout indicator */
#define FM10K_MAXHOLDQ(_n) ((_n) + 0x0020)
/* Switch Manager info */
#define FM10K_SM_AREA(_n) ((_n) + 0x0028)
/* GLORT mapping registers */
#define FM10K_DGLORTMAP(_n) ((_n) + 0x0030)
#define FM10K_DGLORT_COUNT 8
#define FM10K_DGLORTMAP_MASK_SHIFT 16
#define FM10K_DGLORTMAP_ANY 0x00000000
#define FM10K_DGLORTMAP_NONE 0x0000FFFF
#define FM10K_DGLORTMAP_ZERO 0xFFFF0000
#define FM10K_DGLORTDEC(_n) ((_n) + 0x0038)
#define FM10K_DGLORTDEC_VSILENGTH_SHIFT 4
#define FM10K_DGLORTDEC_VSIBASE_SHIFT 7
#define FM10K_DGLORTDEC_PCLENGTH_SHIFT 14
#define FM10K_DGLORTDEC_QBASE_SHIFT 16
#define FM10K_DGLORTDEC_RSSLENGTH_SHIFT 24
#define FM10K_DGLORTDEC_INNERRSS_ENABLE 0x08000000
#define FM10K_TUNNEL_CFG 0x0040
#define FM10K_TUNNEL_CFG_NVGRE_SHIFT 16
#define FM10K_SWPRI_MAP(_n) ((_n) + 0x0050)
#define FM10K_SWPRI_MAX 16
#define FM10K_RSSRK(_n, _m) (((_n) * 0x10) + (_m) + 0x0800)
#define FM10K_RSSRK_SIZE 10
#define FM10K_RSSRK_ENTRIES_PER_REG 4
#define FM10K_RETA(_n, _m) (((_n) * 0x20) + (_m) + 0x1000)
#define FM10K_RETA_SIZE 32
#define FM10K_RETA_ENTRIES_PER_REG 4
#define FM10K_MAX_RSS_INDICES 128
/* Rate limiting registers */
#define FM10K_TC_CREDIT(_n) ((_n) + 0x2000)
#define FM10K_TC_CREDIT_CREDIT_MASK 0x001FFFFF
#define FM10K_TC_MAXCREDIT(_n) ((_n) + 0x2040)
#define FM10K_TC_MAXCREDIT_64K 0x00010000
#define FM10K_TC_RATE(_n) ((_n) + 0x2080)
#define FM10K_TC_RATE_QUANTA_MASK 0x0000FFFF
#define FM10K_TC_RATE_INTERVAL_4US_GEN1 0x00020000
#define FM10K_TC_RATE_INTERVAL_4US_GEN2 0x00040000
#define FM10K_TC_RATE_INTERVAL_4US_GEN3 0x00080000
/* DMA control registers */
#define FM10K_DMA_CTRL 0x20C3
#define FM10K_DMA_CTRL_TX_ENABLE 0x00000001
#define FM10K_DMA_CTRL_TX_ACTIVE 0x00000008
#define FM10K_DMA_CTRL_RX_ENABLE 0x00000010
#define FM10K_DMA_CTRL_RX_ACTIVE 0x00000080
#define FM10K_DMA_CTRL_RX_DESC_SIZE 0x00000100
#define FM10K_DMA_CTRL_MINMSS_64 0x00008000
#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN3 0x04800000
#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN2 0x04000000
#define FM10K_DMA_CTRL_MAX_HOLD_1US_GEN1 0x03800000
#define FM10K_DMA_CTRL_DATAPATH_RESET 0x20000000
#define FM10K_DMA_CTRL_32_DESC 0x00000000
#define FM10K_DMA_CTRL2 0x20C4
#define FM10K_DMA_CTRL2_SWITCH_READY 0x00002000
/* TSO flags configuration
* First packet contains all flags except for fin and psh
* Middle packet contains only urg and ack
* Last packet contains urg, ack, fin, and psh
*/
#define FM10K_TSO_FLAGS_LOW 0x00300FF6
#define FM10K_TSO_FLAGS_HI 0x00000039
#define FM10K_DTXTCPFLGL 0x20C5
#define FM10K_DTXTCPFLGH 0x20C6
#define FM10K_TPH_CTRL 0x20C7
#define FM10K_MRQC(_n) ((_n) + 0x2100)
#define FM10K_MRQC_TCP_IPV4 0x00000001
#define FM10K_MRQC_IPV4 0x00000002
#define FM10K_MRQC_IPV6 0x00000010
#define FM10K_MRQC_TCP_IPV6 0x00000020
#define FM10K_MRQC_UDP_IPV4 0x00000040
#define FM10K_MRQC_UDP_IPV6 0x00000080
#define FM10K_TQMAP(_n) ((_n) + 0x2800)
#define FM10K_TQMAP_TABLE_SIZE 2048
#define FM10K_RQMAP(_n) ((_n) + 0x3000)
/* Hardware Statistics */
#define FM10K_STATS_TIMEOUT 0x3800
#define FM10K_STATS_UR 0x3801
#define FM10K_STATS_CA 0x3802
#define FM10K_STATS_UM 0x3803
#define FM10K_STATS_XEC 0x3804
#define FM10K_STATS_VLAN_DROP 0x3805
#define FM10K_STATS_LOOPBACK_DROP 0x3806
#define FM10K_STATS_NODESC_DROP 0x3807
/* Timesync registers */
#define FM10K_SYSTIME 0x3814
#define FM10K_SYSTIME_CFG 0x3818
#define FM10K_SYSTIME_CFG_STEP_MASK 0x0000000F
/* PCIe state registers */
#define FM10K_PHYADDR 0x381C
/* Rx ring registers */
#defi