jiaotongxinhaodeng.rar_fredevider_jiaotongxinhaodeng_matlab红灯_tr

Debug for fit_fastio_pin_reassign program (iteration 1): I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 45 N/A 51 N/A N/A Clr N/A 45 N/A 51 N/A N/A Pre N/A 41 N/A 47 N/A N/A Ena N/A N/A 19 N/A N/A N/A Ald N/A 41 N/A 47 N/A N/A OE N/A N/A N/A 48 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 24 N/A 93 N/A N/A N/A A N/A N/A 14 30 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 5 24 N/A 12 N/A Clr : N/A 12 N/A N/A 19 N/A Pre : N/A 12 N/A N/A 19 N/A Ena : N/A N/A 16 N/A N/A N/A Ald : N/A 12 N/A N/A 19 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 14 N/A 14 N/A 2 18 Casc: 6 N/A 6 N/A N/A 10 Pin : N/A N/A N/A N/A N/A N/A A : 17 N/A 17 N/A 7 21 B : 16 N/A 16 N/A 7 20 C : 16 N/A 16 N/A N/A 20 D : 14 N/A 14 N/A N/A 18 I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 45 N/A 51 N/A N/A Clr N/A 45 N/A 51 N/A N/A Pre N/A 41 N/A 47 N/A N/A Ena N/A N/A 19 N/A N/A N/A Ald N/A 41 N/A 47 N/A N/A OE N/A N/A N/A 48 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 24 N/A 93 N/A N/A N/A A N/A N/A 14 30 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 5 24 N/A 12 N/A Clr : N/A 12 N/A N/A 19 N/A Pre : N/A 12 N/A N/A 19 N/A Ena : N/A N/A 16 N/A N/A N/A Ald : N/A 12 N/A N/A 19 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 14 N/A 14 N/A 2 18 Casc: 6 N/A 6 N/A N/A 10 Pin : N/A N/A N/A N/A N/A N/A A : 17 N/A 17 N/A 7 21 B : 16 N/A 16 N/A 7 20 C : 16 N/A 16 N/A N/A 20 D : 14 N/A 14 N/A N/A 18 Threshold are: for Tsu - 8.200000ns and for Tco - 14.600000ns Global Tsu=-1(-1.000000), Tco=-1(-1.000000) Input/output cells: A0 : OUT A1 : OUT A2 : OUT A3 : OUT B0 : OUT B1 : OUT B2 : OUT B3 : OUT CLK -> 79 : IN C0 : OUT C1 : OUT C2 : OUT C3 : OUT D0 : OUT D1 : OUT D2 : OUT D3 : OUT GREENA : OUT GREENB : OUT HOLD : IN REDA : OUT REDB : OUT RESET -> 80 : IN YELLOWA : OUT YELLOWB : OUT Set clique dont_touch: Cell: A0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: A1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: A2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: A3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: B3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: CLK, rdfbits: d, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:121, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:125, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:129, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:133, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|LPM_ADD_SUB:160|addcore:adder|:137, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:4, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:6, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:8, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:10, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:12, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:14, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|:16, rdfbits: 800210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|~109~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTER:44|~278~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|LPM_ADD_SUB:261|addcore:adder|pcarry3, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|LPM_ADD_SUB:261|addcore:adder|pcarry4, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:10, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:12, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:14, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:16, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:18, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:20, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:22, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:24, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:26, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:28, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:30, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:32, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:34, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:36, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:38, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:40, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:42, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:44, rdfbits: 210, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:148, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:407, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:422, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:434, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:446, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:458, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|:600, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |COUNTROLLER:49|~820~1, rdfbits: 201050, fast_io bit: 0, periphery: 0,0 Cell: C0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: C1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: C2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: C3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: D3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|LPM_ADD_SUB:388|addcore:adder|pcarry2, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|LPM_ADD_SUB:388|addcore:adder|:92, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|LPM_ADD_SUB:476|addcore:adder|:71, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|~119~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|~119~2, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:119, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:153, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:187, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:223, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:260, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:291, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|~677~1, rdfbits: 201050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:677, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:698, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:710, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:721, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:725, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:728, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:731, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:734, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |FENWEI2:47|:738, rdfb