edma.rar_edma_event_linux EDMA

/* * TI EDMA DMA engine driver * * Copyright 2012 Texas Instruments * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation version 2. * * This program is distributed "as is" WITHOUT ANY WARRANTY of any * kind, whether express or implied; without even the implied warranty * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ #include <linux/dmaengine.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/list.h> #include <linux/module.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/of.h> #include <linux/platform_data/edma.h> #include "dmaengine.h" #include "virt-dma.h" /* * This will go away when the private EDMA API is folded * into this driver and the platform device(s) are * instantiated in the arch code. We can only get away * with this simplification because DA8XX may not be built * in the same kernel image with other DaVinci parts. This * avoids having to sprinkle dmaengine driver platform devices * and data throughout all the existing board files. */ #ifdef CONFIG_ARCH_DAVINCI_DA8XX #define EDMA_CTLRS 2 #define EDMA_CHANS 32 #else #define EDMA_CTLRS 1 #define EDMA_CHANS 64 #endif /* CONFIG_ARCH_DAVINCI_DA8XX */ /* * Max of 20 segments per channel to conserve PaRAM slots * Also note that MAX_NR_SG should be atleast the no.of periods * that are required for ASoC, otherwise DMA prep calls will * fail. Today davinci-pcm is the only user of this driver and * requires atleast 17 slots, so we setup the default to 20. */ #define MAX_NR_SG 20 #define EDMA_MAX_SLOTS MAX_NR_SG #define EDMA_DESCRIPTORS 16 struct edma_pset { u32 len; dma_addr_t addr; struct edmacc_param param; }; struct edma_desc { struct virt_dma_desc vdesc; struct list_head node; enum dma_transfer_direction direction; int cyclic; int absync; int pset_nr; struct edma_chan *echan; int processed; /* * The following 4 elements are used for residue accounting. * * - processed_stat: the number of SG elements we have traversed * so far to cover accounting. This is updated directly to processed * during edma_callback and is always <= processed, because processed * refers to the number of pending transfer (programmed to EDMA * controller), where as processed_stat tracks number of transfers * accounted for so far. * * - residue: The amount of bytes we have left to transfer for this desc * * - residue_stat: The residue in bytes of data we have covered * so far for accounting. This is updated directly to residue * during callbacks to keep it current. * * - sg_len: Tracks the length of the current intermediate transfer, * this is required to update the residue during intermediate transfer * completion callback. */ int processed_stat; u32 sg_len; u32 residue; u32 residue_stat; struct edma_pset pset[0]; }; struct edma_cc; struct edma_chan { struct virt_dma_chan vchan; struct list_head node; struct edma_desc *edesc; struct edma_cc *ecc; int ch_num; bool alloced; int slot[EDMA_MAX_SLOTS]; int missed; struct dma_slave_config cfg; }; struct edma_cc { int ctlr; struct dma_device dma_slave; struct edma_chan slave_chans[EDMA_CHANS]; int num_slave_chans; int dummy_slot; }; static inline struct edma_cc *to_edma_cc(struct dma_device *d) { return container_of(d, struct edma_cc, dma_slave); } static inline struct edma_chan *to_edma_chan(struct dma_chan *c) { return container_of(c, struct edma_chan, vchan.chan); } static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx) { return container_of(tx, struct edma_desc, vdesc.tx); } static void edma_desc_free(struct virt_dma_desc *vdesc) { kfree(container_of(vdesc, struct edma_desc, vdesc)); } /* Dispatch a queued descriptor to the controller (caller holds lock) */ static void edma_execute(struct edma_chan *echan) { struct virt_dma_desc *vdesc; struct edma_desc *edesc; struct device *dev = echan->vchan.chan.device->dev; int i, j, left, nslots; /* If either we processed all psets or we're still not started */ if (!echan->edesc || echan->edesc->pset_nr == echan->edesc->processed) { /* Get next vdesc */ vdesc = vchan_next_desc(&echan->vchan); if (!vdesc) { echan->edesc = NULL; return; } list_del(&vdesc->node); echan->edesc = to_edma_desc(&vdesc->tx); } edesc = echan->edesc; /* Find out how many left */ left = edesc->pset_nr - edesc->processed; nslots = min(MAX_NR_SG, left); edesc->sg_len = 0; /* Write descriptor PaRAM set(s) */ for (i = 0; i < nslots; i++) { j = i + edesc->processed; edma_write_slot(echan->slot[i], &edesc->pset[j].param); edesc->sg_len += edesc->pset[j].len; dev_vdbg(echan->vchan.chan.device->dev, "\n pset[%d]:\n" " chnum\t%d\n" " slot\t%d\n" " opt\t%08x\n" " src\t%08x\n" " dst\t%08x\n" " abcnt\t%08x\n" " ccnt\t%08x\n" " bidx\t%08x\n" " cidx\t%08x\n" " lkrld\t%08x\n", j, echan->ch_num, echan->slot[i], edesc->pset[j].param.opt, edesc->pset[j].param.src, edesc->pset[j].param.dst, edesc->pset[j].param.a_b_cnt, edesc->pset[j].param.ccnt, edesc->pset[j].param.src_dst_bidx, edesc->pset[j].param.src_dst_cidx, edesc->pset[j].param.link_bcntrld); /* Link to the previous slot if not the last set */ if (i != (nslots - 1)) edma_link(echan->slot[i], echan->slot[i+1]); } edesc->processed += nslots; /* * If this is either the last set in a set of SG-list transactions * then setup a link to the dummy slot, this results in all future * events being absorbed and that's OK because we're done */ if (edesc->processed == edesc->pset_nr) { if (edesc->cyclic) edma_link(echan->slot[nslots-1], echan->slot[1]); else edma_link(echan->slot[nslots-1], echan->ecc->dummy_slot); } if (edesc->processed <= MAX_NR_SG) { dev_dbg(dev, "first transfer starting on channel %d\n", echan->ch_num); edma_start(echan->ch_num); } else { dev_dbg(dev, "chan: %d: completed %d elements, resuming\n", echan->ch_num, edesc->processed); edma_resume(echan->ch_num); } /* * This happens due to setup times between intermediate transfers * in long SG lists which have to be broken up into transfers of * MAX_NR_SG */ if (echan->missed) { dev_dbg(dev, "missed event on channel %d\n", echan->ch_num); edma_clean_channel(echan->ch_num); edma_stop(echan->ch_num); edma_start(echan->ch_num); edma_trigger_channel(echan->ch_num); echan->missed = 0; } } static int edma_terminate_all(struct edma_chan *echan) { unsigned long flags; LIST_HEAD(head); spin_lock_irqsave(&echan->vchan.lock, flags); /* * Stop DMA activity: we assume the callback will not be called * after edma_dma() returns (even if it does, it will see * echan->edesc is NULL and exit.) */ if (echan->edesc) { int cyclic = echan->edesc->cyclic; echan->edesc = NULL; edma_stop(echan->ch_num); /* Move the cyclic channel back to default queue */ if (cyclic) edma_assign_channel_eventq(echan->ch_num, EVENTQ_DEFAULT); } vchan_get_all_descriptors(&echan->vchan, &head); spin_unlock_irqrestore(&echan->vchan.lock, flags); vchan_dma_desc_free_list(&echan->vchan, &head); return 0; } static int edma_slave_config(struct edma_chan *echan, struct dma_slave_config *cfg) { if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES || cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES) return -EINVAL; memcpy(&echan->cfg, cfg, sizeof(echan->cfg)); return 0; } static int edma_dma_pause(struct edma_chan *echan) { /* Pause/Resume only allowed with cyclic mode */ if (!echan->edesc || !echan->edesc->cyclic) return -EINVAL; edma_pause(e