ADC-PWM.rar_ADC PWM

#include <p30f2010.h> #include <libpic30.h> #pragma config FOS=FRC // Oscillator Source (Internal Fast RC) int ADCValue1; int ADCValue2; int ADCValue3; int main(void); // Declare Main Function int main(void) { // ***** CONFIGURE 3 OUTPUT PWM ***** PTPER = 0x007A; // 122 Time base register = 126d (=> PDCx Value for 100% Duty Cycle = 254d (2X(PTPER+1)) ) PDC1 = PTPER; // PWM1 value = 50% PDC2 = PTPER; // PWM2 value = 50% PDC3 = PTPER; // PWM3 value = 50% PWMCON1 = 0x0077; // PMOD3:PMOD1 = 0 (PWM I/O pin pairs are in the complementary output mode) // PEN3H-PEN1H = 7 (PWM1H..PWM3H pins are enabled for PWM output) // PEN3L-PEN1L = 7 (PWM1L..PWM3L pins are enabled for PWM output) PWMCON2 = 0x0004; // SEVOPS<3:0> = 0 (PWM Special Event Trigger Output Postscale Select bits = 1:1 (Not Used)) // IUE = 1 (Updates to the active PDC registers are immediate) // OSYNC = 0 (Output overrides via the OVDCON register occur on next TCY boundary) // UDIS = 0 (Updates from duty cycle and period buffer registers are enabled) //PTCON = 0x800C; // PTEN = 1 (PWM time base is ON) // PTSIDL = 0 (PWM time base runs in CPU Idle mode) // PTOPS<3:0> = 0 (PWM Time Base Output Postscale Select bits = 1:1 Postscale) // PTCKPS<1:0> = 3 (PWM Time Base Input Clock Prescale Select bits => clock period is 64 TCY (1:64 prescale)) // PTMOD<1:0> = 0 (PWM Time Base Mode Select bits => PWM time base operates in a free running mode) // If internal 7.37 MHz oscillator is used => // PWM Frequency = FOSC/(4*PTMRPrescaler*(PTPER+1)) // PWM Frequency = 7.37e6/(4*64*(126+1) = 226.7 Hz // PWM Duty Cycle [%] = 100*(2*PDCx)/(PTPER+1) PTCON=0x8000; // 1:1prescale PTPER=(FOSC/(4*PTMRRrescaler*PWM Frequency))-1= // PTPER= (7.37e6/4*1*15e3)-1)=122 DTCON1= 0x0005; // deadtime=DTCON1value*Tcy = 2us // ***** CONFIGURE 3 INPUT ADC ***** ADPCFG = 0x0030; // PCFG<15:0>: Analog Input Pin Configuration Control bits // 1 = Analog input pin in Digital mode, port read input enabled, A/D input multiplexer input connected to AVSS // 00 = Analog input pin in Analog mode, port read input disabled, A/D samples pin voltage // RB4..RB5 = digital QEI ADCON1 = 0x00EC; // ADON: A/D Operating Mode bit = 0 (A/D Converter is off) // ADSIDL : Stop in idle mode bit = 0 (Continue module operation in idle mode) // FORM<1:0> : Data Output Format bits = 0 (Integer 10 bits) // SSRC<2:0>: Conversion Trigger Source Select bits = 7 (Internal counter ends sampling and starts conversion (auto convert)) // SIMSAM bit : Simultaneous Sample Select bit = 1 implies ... // Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS = 1x) // or // Samples CH0 and CH1 simultaneously (when CHPS = 01) // ASAM : A/D Sample Auto-Start bit = 1 (for auto sample after convert) ADCON2 = 0xE308; // VCFG<2:0> : Voltage Reference Configuration Configuration bits = 7 (Reference Voltages = AVdd/AVss) // CSCNA bit : Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit = 0 (Do Not Scan inputs) // CHPS<1:0> : Selects Channels Utilized bits = 1x implies simultaneous ... // sample CH0 to CH3 // SMPI<3:0> : Sample/Convert Sequences Per Interrupt Selection bits = 2 for interrupt after 3 converts // BUFM : Buffer Mode Select bit = 0 (Buffer configured as one 16-word buffer ADCBUF(15...0.)) // ALTS: Alternate Input Sample Mode Select bit = 0 (Always use MUX A input multiplexer settings) ADCON3 = 0x0302; // SAMC<4:0>: Auto-Sample Time bits = 3 (3 Tad) // ADRC: A/D Conversion Clock Source bit = 0 (Clock derived from system clock) // ADCS<5:0>: A/D Conversion Clock Select bits = 2 (2 TCY) ADCHS = 0x0020; // CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for MUX A Multiplexer Setting bits = 0 (CH1, CH2, CH3 negative input is VREF-) // CH123SA: Channel 1, 2, 3 Positive Input Select for MUX A Multiplexer Setting bit = 1 implies... // CH1 = AN3 / CH2 = AN4 / CH3 = AN5 // ADCBUF1 = AN3 / ADCBUF2 = AN4 / ADCBUF3 = AN5 // CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit = 0 (Channel 0 negative input is VREF-) // CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits = 0 implies... // Connect AN0 as CH0 input => ADCBUF0 = AN0 ADCSSL = 0; // CSSL<15:0>: A/D Input Pin Scan Selection bits // 1 = Select ANx for input scan // 0 = Skip ANx for input scan // ***NOT USED*** ADCON1bits.ADON = 1; // turn ADC ON /// INITIALIZING THE QEI MODULE QEICONbits.QEIM = 0; // Disable QEI Module QEICONbits.CNTERR = 0; // Clear any count errors QEICONbits.QEISIDL = 0; // Continue operation during sleep QEICONbits.SWPAB = 0; // QEA and QEB not swapped QEICONbits.PCDOUT = 0; // Normal I/O pin operation QEICONbits.POSRES = 1; // Index pulse resets position counter POSRES=0 if QEIM=111 reset by MAXCNT DFLTCONbits.CEID = 1; // Count error interrupts disabled DFLTCONbits.QEOUT = 1; // Digital filters output enabled for QEn pins DFLTCONbits.QECK = 5; // 1:64 clock divide for digital filter for QEn //DFLTCONbits.INDOUT = 1; // Digital filter output enabled for Index pin //DFLTCONbits.INDCK = 5; // 1:64 clock divide for digital filter for Index POSCNT = 0; // Reset position counter QEICONbits.QEIM = 6; // X4 mode with position counter reset by Index or QEIM=111 position reset MAXCNT if 3rd pin encoder INDEX is not present // ***** MAIN BLOCK ***** while (1) // repeat continuously { while (!ADCON1bits.DONE); // conversion done? { } ADCValue1 = ADCBUF0; // yes then get ADC value ADCValue2 = ADCBUF2; // yes then get ADC value ADCValue3 = ADCBUF3; // yes then get ADC value PDC1 = (ADCValue1>>2); // RED LED Duty Cycle = 10bits Result/4 (10bits => 8Bits) of AN3 PDC2 = (ADCValue2>>2); // GREEN LED Duty Cycle = 10bits Result/4 (10bits => 8Bits) of AN1 PDC3 = (ADCValue3>>2); // BLUE LED Duty Cycle = 10bits Result/4 (10bits => 8Bits) of AN2