uart.rar_6748串口_TMS320C6748_c6748 UART_c6748 UARTGets_tms320c67

/** * \file interrupt.c * * \brief Contains DSP interrupt related APIs. */ /* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions * are met: * * Redistributions of source code must retain the above copyright * notice, this list of conditions and the following disclaimer. * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the * distribution. * * Neither the name of Texas Instruments Incorporated nor the names of * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ #include <c6x.h> #include "interrupt.h" /****************************************************************************** ** INTERNAL DEFINES ******************************************************************************/ #define C674X_NMI 1 #define C674X_GEE 2 #define C674X_XEN 3 #define C674X_INT_COUNT 16 #define NUM_SYS_EVENTS 128 /****************************************************************************** ** EXTERNALLY DEFINED FUNCTIONS ******************************************************************************/ #ifdef __TI_EABI__ extern void _intcVectorTable (void); #else extern void intcVectorTable (void); #endif /****************************************************************************** ** STATIC VARIABLES/FUNCTIONS ******************************************************************************/ static c674xISR c674xISRtbl[C674X_INT_COUNT]; static c674xISR c674xECMtbl[NUM_SYS_EVENTS]; static void IntDefaultHandler (void); static void IntEventCombineIsr0 (void); static void IntEventCombineIsr1 (void); static void IntEventCombineIsr2 (void); static void IntEventCombineIsr3 (void); static void IntEventCombinerDispatch (unsigned int evtReg); /****************************************************************************** ** API INTERRUPT FUNCTIONS ******************************************************************************/ /** * \function IntDSPINTCInit * * \brief This API is used to setup the DSP Interrupt Controller (INTC) * and should be called before using the DSP INTC. All CPU * maskable interrupts will be disabled after calling this API and * the user should proceed to setup the required interrupts for * processing. * * \param None * * \return None */ void IntDSPINTCInit (void) { unsigned int step = 0; /* Set ISRs to default "do-nothing" routine */ while(step != C674X_INT_COUNT) c674xISRtbl[step++] = IntDefaultHandler; /* Set interrupt service table pointer to the vector table */ #ifdef __TI_EABI__ ISTP = (unsigned int)_intcVectorTable; #else ISTP = (unsigned int)intcVectorTable; #endif /* Clear pending CPU maskable interrupts (if any) */ ICR = 0xFFF0; /* Enable NMIE bit to allow CPU maskable interrupts */ IER = (1 << C674X_NMI); } /** * \function IntRegister * * \brief Registers an interrupt service routine in the interrupt * vector table for CPU maskable interrupts, NMI, or * reserved interrupts. * * \param cpuINT - CPU maskable interrupt number (4-15), NMI (1), * or reserved interrupt (2-3) * \param userISR - Function pointer to the ISR * * \return None */ void IntRegister (unsigned int cpuINT, void (*userISR)(void)) { /* Check the CPU maskable interrupt number */ ASSERT(((cpuINT >= 1) && (cpuINT <= 15))); /* Assign the user's ISR to the CPU maskable interrupt */ c674xISRtbl[cpuINT] = userISR; } /** * \function IntUnRegister * * \brief Unregisters an interrupt. * * \param cpuINT - CPU maskable interrupt number (4-15), NMI (1), * or reserved interrupt (2-3) * * \return None */ void IntUnRegister (unsigned int cpuINT) { /* Check the CPU maskable interrupt number */ ASSERT(((cpuINT >= 1) && (cpuINT <= 15))); /* Assign the default "do-nothing" routine to the CPU maskable interrupt */ c674xISRtbl[cpuINT] = IntDefaultHandler; } /** * \function IntEventMap * * \brief This API maps a system event to a CPU maskable interrupt. * * \param cpuINT - CPU maskable interrupt number * \param sysINT - System event number * * \return None */ void IntEventMap (unsigned int cpuINT, unsigned int sysINT) { unsigned int dspintcREG, restoreVal; /* Check the CPU maskable interrupt number */ ASSERT(((cpuINT >= 4) && (cpuINT <= 15))); /* Check the system event number */ ASSERT((sysINT <= 127)); /* Get the address of the correct interrupt mux register */ dspintcREG = SOC_INTC_0_REGS + DSPINTC_INTMUX((cpuINT >> 2)); /* Disable interrupts */ restoreVal = IntGlobalDisable(); /* Clear and set INTSELx with system event number */ HWREG(dspintcREG) = (HWREG(dspintcREG) & ~DSPINTC_INTMUX_INTSEL(cpuINT)) | (sysINT << DSPINTC_INTMUX_INTSEL_SHIFT(cpuINT)); /* Clear any residual interrupt */ ICR = (1 << cpuINT); /* Restore interrupts */ IntGlobalRestore(restoreVal); } /** * \function IntEventSet * * \brief This API manually sets a system event in the event flag * register. * * \param sysINT - System event number * * \return None */ void IntEventSet (unsigned int sysINT) { unsigned int dspintcREG; /* Check the system event number */ ASSERT((sysINT <= 127)); /* Get the address of the correct event register */ dspintcREG = SOC_INTC_0_REGS + DSPINTC_EVTSET((sysINT >> 5)); /* Set the corresponding bit within the event flag register */ HWREG(dspintcREG) = DSPINTC_EVTSET_ES(sysINT); } /** * \function IntEventClear * * \brief This API clears the system interrupt status in the DSP * interrupt controller. * * \param sysINT - System event number * * \return None */ void IntEventClear(unsigned int sysINT) { unsigned int dspintcREG; /* Check the system event number */ ASSERT((sysINT <= 127)); /* Get the address of the correct event register */ dspintcREG = SOC_INTC_0_REGS + DSPINTC_EVTCLR((sysINT >> 5)); /* Clear the corresponding bit within the event clear register */ HWREG(dspintcREG) = DSPINTC_EVTCLR_EC(sysINT); } /** * \function IntEventCombineInit * * \brief This API removes all system events from the ECM, assigns * the event ISRs to a default handler, registers the ECM * ISR to the corresponding CPU interrupt, maps the ECM * system event to the corresponding CPU interrupt, and