dsl.rar_dsl

4.8 module shifter(din,clk,clr,dout); `define size 7 input din,clk,clr; output[`size:0]dout; reg[`size:0]dout; always@(posedge clk) begin if(clr) dout=0; else begin dout=dout<<1'b1; dout[0]=din; end end endmodule 4.9 module secq(clk,clr,dout); input clk,clr; output dout; reg dout; reg[7,0] reg_a always@(posedge clk) if(clr) begin dout<=1'b0; reg_a<=8'b10110101; end else begin reg_a<={reg_a[6:0],reg_a[7]}; dout<=reg_a[7]; end endmodule 4.10 module div(clk,clr,div2,div4,div8,div16); input clk,clr; output div2,div4,div8,div16; reg[3:0]cnt; always@(posedge clk) if(clr)cnt<=4b'0; else cnt<=cnt+1'b1; assign{div16,div8,div4,div2}=cnt; endmodule 4.11 module div12(clk,clr,div12); input clk,clr; output div12; reg div12; reg[3:0]cnt; always@(posedge clk) if(clr) begin cnt<=4'b0; div12<=1'b0; end else if(cnt==4'd11) begin div12<=1'b1; cnt<=4'b0; end else begin cnt<=cnt+1'b1; div12<=1'b0; end endmodule 4.12 module test(clk,div5); input clk; output div5; reg[3:0]cnt_up,cnt_down; reg cnt_up_h,cnt_down_h; always@(posedge clk) if(cnt_up==3'd4)cnt_up<=3'b0; else cnt_up<=cnt_up+1'b1; always@(negedge clk) if(cnt_down==3'd4) cnt_down<=3'b0; else cnt_down<=cnt_down+1'b1; always@(negedge clk) if(cnt_up<3'b010)cnt_up_h<=1'b1; else cnt_up_h<=1'b0; always@(negedge clk) if(cnt_down<3'b010) cnt_down_h<=1'b1; else cnt_down_h<=1'b0; assign div5=cnt_up_h|cnt_down_h; endmodule 4.13 module fsm_110(data,clk,nclr,out); input data,clk,nclr; output out; reg out; reg[2:0]current_state,next_state; parameter[1:0]s0=0,s1=1,s2=2,s3=3; always@(pwsedge clk) if(!nclr) current_state<=s0; else current_state<=next_state; always@(current_state or data) case(current_state) s0: next_state=(data==1'b1)?s1:s0; s1: next_state=(data==1'b1)?s2:s0; s2: next_state=(data==1'b1)?s2:s3; s3: next_state=(data==1'b1)?s1:s0; endcase always@(current_state or data) case(current_state) s0: out=1'b0; s1: out=1'b0; s2: out=(data==1'b1)?1'b0:1'b1; s3: out=1'b0; endcase endmodule 4:14 module add8(cout,sum,a,b,cin); output[7:0] sum; output cout; input[7:0] a,b; input cin; assign{cout,sum}=a+b+cin; endmodule module reg8(qout,in,clk,clr); output[7:0] qout; input[7:0] in; input clk,clr; reg[7:0] qout; always@(posedge clk or posedge clr) if(clr) qout=0; else qout=in; endmodule module acc(accout,cout,areg,cin,clk,clr); output[7:0] accout; output cout; input[7:0] areg; input clk,clr,cin; wire[7:0] sum; add8 acc_add8(cout,sum,areg,accout,cin); reg8 acc_reg8(accout,sum,clk,clr); endmodule `include "add8.v" `include "reg8.v" module acc(accout,cout,areg,cin,clk,clr); output[7:0] accout; aoutput cout; input[7:0] areg; input clk,clr,cin; wire[7:0] sum; add8 acc_add8(cout,sum,areg,accout,cin); reg8 acc_reg8(.qout(accout),.clr(clr),.in(sum),.clk(clk)); endmodule //tonetable module tonetable(clk4hz,predata); input clk4hz; output[12:0]predata; reg[12:0]predata; parameter low_3=13'7583; parameter low_5=13'6377; parameter low_6=13'5681; parameter low_7=13'5062; parameter mid_1=13'4777; parameter mid_2=13'4256; parameter mid_3=13'3791; parameter mid_5=13'3188; parameter mid_6=13'2840; parameter high_3=13'2391; parameter stop=13'd0; reg [7:0] counter; always@(posedge clk4hz) if(counter>=135) counter=8'b0; else counter=counter+1'b1; always@(counter) case (counter) 8'd0: predata=low_3; 8'd1: predata=low_3; 8'd2: predata=low_3; 8'd3: predata=low_3; 8'd4: predata=low_5; 8'd5: predata=low_5; 8'd6: predata=low_5; 8'd7: predata=low_6; 8'd8: predata=mid_1; 8'd9: predata=mid_1; 8'd10: predata=mid_1; 8'd11: predata=mid_2; 8'd12: predata=low_6; 8'd13: predata=mid_1; 8'd14: predata=low_5; 8'd15: predata=low_5; 8'd16: predata=mid_5; 8'd17: predata=mid_5; 8'd18: predata=mid_5; 8'd19: predata=high_1; 8'd20: predata=mid_6; 8'd21: predata=mid_5; 8'd22: predata=mid_3; 8'd23: predata=mid_5; 8'd24: predata=mid_2; 8'd25: predata=mid_2; 8'd26: predata=mid_2; 8'd27: predata=mid_2; 8'd28: predata=mid_2; 8'd29: predata=mid_2; 8'd30: predata=mid_2; 8'd31: predata=mid_2; 8'd32: predata=mid_2; 8'd33: predata=mid_2; 8'd34: predata=mid_2; 8'd35: predata=mid_3; 8'd36: predata=low_7; 8'd37: predata=low_7; 8'd38: predata=low_6; 8'd39: predata=low_6; 8'd40: predata=low_5; 8'd41: predata=low_5; 8'd42: predata=low_5; 8'd43: predata=low_6; 8'd44: predata=mid_1; 8'd45: predata=mid_1; 8'd46: predata=mid_2; 8'd47: predata=mid_2; 8'd48: predata=mid_3; 8'd49: predata=mid_3; 8'd50: predata=mid_1; 8'd51: predata=mid_1; 8'd52: predata=mid_6; 8'd53: predata=mid_5; 8'd54: predata=mid_6; 8'd55: predata=mid_1; 8'd56: predata=low_5; 8'd57: predata=low_5; 8'd58: predata=low_5; 8'd59: predata=low_5; 8'd60: predata=mid_3; 8'd61: predata=mid_3; 8'd62: predata=mid_3; 8'd63: predata=mid_5; 8'd64: predata=low_7; 8'd65: predata=low_7; 8'd66: predata=low_7; 8'd67: predata=mid_2; 8'd68: predata=low_6; 8'd69: predata=mid_1; 8'd70: predata=low_5; 8'd71: predata=low_5; 8'd72: predata=low_5; 8'd73: predata=low_5; 8'd74: predata=low_5; 8'd75: predata=low_5; 8'd76: predata=low_3; 8'd77: predata=low_5; 8'd78: predata=low_3; 8'd79: predata=low_3; 8'd80: predata=low_5; 8'd81: predata=low_6; 8'd82: predata=low_7; 8'd83: predata=mid_2; 8'd84: predata=low_6; 8'd85: predata=low_6; 8'd86: predata=low_6; 8'd87: predata=low_6; 8'd88: predata=low_6; 8'd89: predata=low_6; 8'd90: predata=low_5; 8'd91: predata=low_6; 8'd92: predata=mid_1; 8'd93: predata=mid_1; 8'd94: predata=mid_1; 8'd95: predata=mid_2; 8'd96: predata=mid_5; 8'd97: predata=mid_5; 8'd98: predata=mid_3; 8'd99: predata=mid_3; 8'd100: predata=mid_2; 8'd101: predata=mid_2; 8'd102: predata=mid_3; 8'd103: predata=mid_2; 8'd104: predata=mid_1; 8'd105: predata=mid_1; 8'd106: predata=low_6; 8'd107: predata=low_5; 8'd108: predata=low_3; 8'd109: predata=low_3; 8'd110: predata=low_3; 8'd111: predata=low_3; 8'd112: predata=mid_1; 8'd113: predata=mid_1; 8'd114: predata=mid_1; 8'd115: predata=mid_1; 8'd116: predata=low_6; 8'd117: predata=mid_1; 8'd118: predata=low_6; 8'd119: predata=low_5; 8'd120: predata=low_3; 8'd121: predata=low_5; 8'd122: predata=low_6; 8'd123: predata=mid_1; 8'd124: predata=low_5; 8'd125: predata=low_5; 8'd126: predata=low_5; 8'd127: predata=low_5; 8'd128: predata=low_5; 8'd129: predata=low_5; 8'd130: predata=low_5; 8'd131: predata=low_5; 8'd132: predata=stop; 8'd133: predata=stop; 8'd134: predata=stop; 8'd135: predata=stop; default: predata=8'b0; endcase endmodule