--DDS 顶层设计:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dds is
port(
kongzhi:in std_logic_vector(1 downto 0);
fudu:in integer range 0 to 1000;
faa:in std_logic_vector(7 downto 0);
CIN:in std_logic;
CO:out std_logic;
clk:in std_logic;
fbzk:in std_logic_vector(5 downto 0);
chu1:out integer range 0 to 1000000;
chu2:out integer range 0 to 1000000;
chu3:out integer range 0 to 1000000;
chu4:out integer range 0 to 1000000);
END dds;
architecture dingceng of dds IS
component jiafa
port (
CIN:IN STD_LOGIC;
faa:in std_logic_vector(7 downto 0);
fbb:in std_logic_vector(7 downto 0);
CO:OUT STD_LOGIC;
fout:out std_logic_vector(7 downto 0));
end component;
component jcq
port (
clk:in std_logic;
D:in std_logic_vector(7 downto 0);
Q:out std_logic_vector(7 downto 0));
end component;
component rom_sin
port(
ru:in std_logic_vector(5 downto 0);
kongzhi:in std_logic_vector(1 downto 0);
chu:out integer range 0 to 1000);
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