P. A. Franaszek
• This is the original IBM publication. A very technical document that provides more
that most want to know about 8b/10b coding. However, this is where it all began.
• United States Patent Number 4,486,739, December 4, 1984
• This is the patent document. Note that our project references the figures contained
in the patent, so you probably would like to have this on hand. You can purchase a
downloadable PDF very inexpensively from the US Patent Office.
• Cypress CYP15G0401TB Data Sheet, Document #: 38-02112, Cypress
Semiconductor
• This document, describing a commercial Cypress physical layer device that
incorporates 8b/10b, does contain the complete 8b/10b coding tables. This is very
useful for reference during verification.
• Actel, Altera, Lattice and Xilinx all have on-line documents that describe commercially
available 8b/10b cores specifically for their devices. These are useful references for
investigating additional features found in commercial cores.
8b10b_encdec Project Description
There are four VHDL modules in the 8b10b_encdec project::
• 8b10b_enc.vhd
• 8b10b_dec.vhd
• enc_8b10b_TB.vhd
• encdec_8b10b_TB.vhd
8b10b_enc.vhd
This is the encoder module. It is synthesizable VHDL'93. It accepts an 8-bit parallel raw
(unencoded) data character consisting of bits HI, GI, FI, EI, DI, CI, BI, AI. AI is the least
significant bit. There is also an input bit, KI, that indicates that the character input should be
encoded as one of the 12 allowable control, or “K”, characters. All of the inputs are
synchronized to an input clock, “SBYTECLK” as follows:
Bits KI, HI, GI and FI are latched internally on the falling edge of the SBYTECLK.
Bits EI, DI, CI, BI, AI are latched internally on the rising edge of the SBYTECLK
The encoding operation is as described in the original paper and patent. The MS 3 character
bits are encoded by an internal 3b/4b encoder and the disparity, or difference in 1's and 0's is
determined. The 5 LS bits are encoded by an internal 4b/5b encoder depending upon the
disparity value from the previous 3b/4b coding. Likewise, subsequent coding depends upon
the “running disparity value” from the previous coding.
The staggered operation of the encoder was designed so that, a serial bit stream could be
contiguously output by an associated serializer as the encoding took place, therefore
speeding up the process and reducing the need for buffering.