LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY COUNT IS
PORT(
CLK : IN STD_LOGIC;
Q : BUFFER INTEGER RANGE 1 to 4
);
END COUNT;
ARCHITECTURE one OF COUNT IS
BEGIN
PROCESS(clk)
BEGIN
IF CLK'EVENT AND CLK='0' then
IF Q=4 THEN Q<=1;
ELSE Q<=Q+1;
END if;
END if;
END PROCESS;
END one;
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY COUNT4 IS
PORT(
CLR,EN,CLK : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
CO : OUT STD_LOGIC);
END COUNT4;
ARCHITECTURE one OF COUNT4 IS
SIGNAL QQ : STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
PROCESS(CLR,EN,clk)
BEGIN
IF CLR='0' THEN QQ<="001";
ELSIF CLK'EVENT AND CLK='1' then
IF EN='1' THEN
QQ<=QQ+'1';
END if;
END if;
IF QQ=5 THEN CO<='1';
ELSE CO<='0';
END if;
Q<=QQ;
