DTC.rar_DTC 程序_DTC代码_dtc_直接转矩_转矩

;************************************************************* ; File Name: F240_app.h ; Originator: Digital Control Systems ; Texas Instruments ; ; Description: ;-------------------------------------------------------------- ; On Chip Periperal Register Definitions ;-------------------------------------------------------------- ;F240 Core Registers ;~~~~~~~~~~~~~~~~~~~~ IMR .set 0004h ; Int Mask GREG .set 0005h ; Global memory allocation IFR .set 0006h ; Int Flag ABRPT .set 01fh ; Analysis BreakPoint WSGR .set 0FFFFh ; Wait State Control (IO space mapped) ;System Module Registers ;~~~~~~~~~~~~~~~~~~~~~~~ SYSCR .set 7018h ; System Control (f240 ) SYSSR .set 701Ah ; System Status (f240 ) SYSIVR .set 701Eh ; System Int Vector (f240 ) DIN .set 0701Ch ; Device Identification Register ; External interrupt configuration registers XINT1CR240 .set 7070h ; Int1 (type A) config (f240 ) XINT2CR240 .set 7078h ; Int2 (type C) config (f240 ) XINT3CR240 .set 707Ah ; Int3 (type C) config (f240 ) NMICR .set 7072h ; NMI (type A) config (f240 ) XINT1_CNTL .set 07070h ;Int1 (type A) Control reg NMI_CNTL .set 07072h ;Non maskable Int (type A) Control reg XINT2_CNTL .set 07078h ;Int2 (type C) Control reg XINT3_CNTL .set 0707Ah ;Int3 (type C) Control reg ; PLL configuration registers - f240 CKCR0 .set 702ah ; PLL Clock Control 0 (f240 ) CKCR1 .set 702ch ; PLL Clock Control 1 (f240 ) ;Digital I/O ;~~~~~~~~~~~ OCRA .set 07090h ; Output Control A MCRA .set 07090h ;I/O Mux Control Reg A OCRB .set 07092h ; Output Control B MCRB .set 07092h ;I/O Mux Control Reg B ISRA .set 7094h ; Input Status A (f240 ) ISRB .set 7096h ; Input Status B (f240 ) PADATDIR .set 07098h ; I/O port A Data & Direction PBDATDIR .set 0709Ah ; I/O port B Data & Direction PCDATDIR .set 0709Ch ; I/O port C Data & Direction PDDATDIR .set 0709Eh ;I/O port D Data & Direction reg. PEDATDIR .set 07095h ; I/O port D Data & Direction PFDATDIR .set 07096h ; I/O port D Data & Direction ;Watch-Dog(WD) / Real Time Int(RTI) / Phase Lock Loop(PLL) Registers ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ RTI_CNTR .set 07021h ; RTI Counter reg WD_CNTR .set 07023h ; WD Counter reg WD_KEY .set 07025h ; WD Key reg WDKEY .set WD_KEY RTI_CNTL .set 07027h ; RTI Control reg WD_CNTL .set 07029h ; WD Control reg WDCR .set WD_CNTL PLL_CNTL1 .set 0702Bh ; PLL control reg 1 PLL_CNTL2 .set 0702Dh ; PLL control reg 2 ;Analog-to-Digital Converter(ADC) registers - x240/1/2/3 ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ADC_CNTL1 .set 07032h ; ADC Control reg 1 ADC_CNTL2 .set 07034h ; ADC Control reg 2 ADC_FIFO1 .set 07036h ; ADC FIFO data reg 1 ADC_FIFO2 .set 07038h ; ADC FIFO data reg 2 ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ;Serial Peripheral Interface (SPI) Registers ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SPI_CCR .set 07040h ;SPI Config Control Reg 1 SPI_CTL .set 07041h ;SPI Operation Control Reg 2 SPI_STS .set 07042h ;SPI Status Reg SPI_BRR .set 07044h ;SPI Baud rate control reg SPI_EMU .set 07046h ;SPI Emulation buffer reg SPI_BUF .set 07047h ;SPI Serial Input buffer reg SPI_DAT .set 07049h ;SPI Serial Data reg SPI_PC1 .set 0704Dh ;SPI Port control reg1 SPI_PC2 .set 0704Eh ;SPI Port control reg2 SPI_PRI .set 0704Fh ;SPI Priority control reg ;Serial Communications Interface (SCI) Registers ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ SCICCR .set 07050h ;SCI Comms Control Reg SCICNTL1 .set 07051h ;SCI Control Reg 1 SCIHBAUD .set 07052h ;SCI Baud rate control SCILBAUD .set 07053h ;SCI Baud rate control SCICNTL2 .set 07054h ;SCI Control Reg 2 SCIRXTX .set 07055h ;SCI Receive status reg SCIRXEMU .set 07056h ;SCI EMU data buffer SCIRXBUF .set 07057h ;SCI Receive data buffer SCITXBUF .set 07059h ;SCI Transmit data buffer SCIPC1 .set 0705Dh ;SCI Port control reg1 SCIPC2 .set 0705Eh ;SCI Port control reg2 SCI_PRI .set 0705Fh ;SCI Priority control reg ;Event Manager (EV)/Event Manager A (EVA) Registers ;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ GPTCON .set 07400h ; General Timer Control T1CNT .set 07401h ; T1 Counter T1CMP .set 07402h ; T1 Compare Value T1PER .set 07403h ; T1 Period T1CON .set 07404h ; T1 Control T2CNT .set 07405h ; T2 Counter T2CMP .set 07406h ; T2 Compare Value T2PER .set 07407h ; T2 Period T2CON .set 07408h ; T2 Control T3CNT .set 07409h ; T3 Counter (240 Only) T3CMP .set 0740ah ; T3 Compare (240 Only) T3PER .set 0740bh ; T3 Period (240 Only) T3CON .set 0740ch ; T3 Control (240 Only) COMCON .set 07411h ; Compare Control ACTR .set 07413h ; Compare Output Action Control (240 Only) SACTR .set 07414h ; S Comp Output Action Control (240 Only) DBTCON .set 07415h ; Dead Band Control CMPR1 .set 07417h ; Compare Value 1 CMPR2 .set 07418h ; Compare Value 2 CMPR3 .set 07419h ; Compare Value 3 SCMPR1 .set 0741ah ; S Comp Value 1 (240 Only) SCMPR2 .set 0741bh ; S Comp Value 2 (240 Only) SCMPR3 .set 0741ch ; S Comp Value 3 (240 Only) CAPCON .set 07420h ; Capture Control CAPCONA .set 07420h ; Capture Control CAPFIFO .set 07422h ; Capture FIFO1-3/4 Status FIFO1 .set 07423h ; Capture 1 FIFO Top FIFO2 .set 07424h ; Capture 2 FIFO Top FIFO3 .set 07425h ; Capture 3 FIFO Top FIFO4 .set 07426h ; Capture 4 FIFO Top (240 Only) IMRA .set 0742ch ; Group A Int Mask IMRB .set 0742dh ; Group B Int Mask IMRC .set 0742eh ; Group C Int Mask EVIMRA .set 0742Ch ; Group A Int Mask EVIMRB .set 0742Dh ; Group B Int Mask EVIMRC .set 0742Eh ; Group C Int Mask EVAIMRA .set 0742Ch ; Group A Int Mask EVAIMRB .set 0742Dh ; Group B Int Mask EVAIMRC .set 0742Eh ; Group C Int Mask IFRA .set 0742fh ; Group A Int Flag IFRB .set 07430h ; Group B Int Flag IFRC .set 07431h ; Group C Int Flag EVIFRA .set 0742Fh ; Group A Int Flag EVIFRB .set 07430h ; Group B Int Flag EVIFRC .set 07431h ; Group C Int Flag EVAIFRA .set 0742Fh ; Group A Int Flag EVAIFRB .set 07430h ; Group B Int Flag EVAIFRC .set 07431h ; Group C Int Flag IVRA .set 07432h ; Group A Int ID (x240 ) IVRB .set 07433h ; Group B Int ID (x240 ) IVRC .set 07434h ; Group C Int ID (x240 ) EVIVRA .set 07432h ; Group A Int ID (x240 ) EVIVRB .set 07433h ; Group B Int ID (x240 ) EVIVRC .set 07434h ; Group C Int ID (x240 ) ;----------------------------------------------------------------------------- ; Constant defines ;----------------------------------------------------------------------------- B0_SADDR .set 00200h ;Block B0 start address B0_EADDR .set 002FFh ;Block B0 end address B1_SADDR .set 00300h ;Block B1 start address B1_EADDR .set 003FFh ;Block B1 end address B2_SADDR .set 00060h ;Block B2 start address B2_EADDR .set 0007Fh ;Block B2 end address ;Bit codes for Test bit instruction (BIT) BIT15 .set 0000h ;Bit Code for 15 BIT14 .set 0001h ;Bit Code for 14 BIT13 .set 0002h ;Bit Code for 13 BIT12 .set 0003h ;Bit Code for 12 BIT11 .set 0004h ;Bit Code for 11 BIT10 .set 0005h ;Bit Code for 10 BIT9 .set 0006h ;Bit Code for 9 BIT8 .set 0007h ;Bit Code for 8 BIT7 .set 0008h ;Bit Code for 7 BIT6 .set 0009h ;Bit Code for 6 BIT5 .set 000Ah ;Bit Code for 5 BIT4 .set 000Bh ;Bit Code for 4 BIT3 .set 000Ch ;Bit Code for 3 BIT2 .set 000Dh ;Bit Code for 2 BIT1 .set 000Eh ;Bit Code for 1 BIT0 .set 000Fh ;Bit Code for 0 ; Used by the SBIT0 & SBIT1 Macro B15_MSK .set 8000h ;Bit Mask for 15 B14_MSK .set 4000h ;Bit Mask for 14 B13_MSK .set 2000h ;Bit Mask for 13 B12_MSK .set 1000h ;Bit Mask for 12 B11_MSK .set 0800h ;Bit Mask for 11 B10_MSK .set 0400h ;Bit Mask for 10 B9_MSK .set 0200h ;Bit Mask for 9 B8_MSK .set 0100h ;Bit Mask for 8 B7_MSK .set 0080h ;Bit Mask for 7 B6_MSK .set 0040h ;Bit Mask for 6 B5_MSK .set 0020h ;Bit Mask for 5 B4_MSK .set 0010h ;Bit Mask for 4