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------------------------------------- -- Title: VGA彩条发生器 -- -- Author:Pan hongtao -- -- Data: 2006-10-1 -- ------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; -------------------------------------------------------------------- entity exp17 is port( Clk : in std_logic; --时钟信号 Key : in std_logic; --模式选择 HS,VS : buffer std_logic; --行同步和场同步 R,G,B : out std_logic --颜色输出 ); end exp17; -------------------------------------------------------------------- architecture behave of exp17 is signal fclk,cclk : std_logic; signal mmd : std_logic_vector(1 downto 0); --mode select signal fs : std_logic_vector(3 downto 0); signal cc : std_logic_vector(4 downto 0); --Horizontal Synchronization signal ll : std_logic_vector(8 downto 0); --Vertical Synchronization signal grbx : std_logic_vector(2 downto 0); --horizontal strip of X signal grby : std_logic_vector(2 downto 0); --vertical strip of Y signal grbp : std_logic_vector(2 downto 0); signal delay : std_logic_vector(15 downto 0); begin B<=grbp(0) and HS and VS; R<=grbp(1) and HS and VS; G<=grbp(2) and HS and VS; process(Clk) --mode of strip generation begin if(Clk'event and Clk='1') then if(Key='0') then if(delay<60000) then delay<=delay+1; end if; else delay<="0000000000000000"; end if; if(delay=10000 and mmd<3) then mmd<=mmd+1; elsif(mmd=3) then mmd<="00"; end if; end if; end process; process(mmd) begin case mmd is when "00"=>grbp<=grbx; --choose horizontal strip when "01"=>grbp<=grby; --choose vertical strip when "10"=>grbp<=grbx xor grby; --choose tessellated designation when others=>grbp<="000"; end case; end process; process(Clk) begin if(Clk'event and Clk='1') then --12MHz clock signal devided by 13 if(fs=12) then fs<="0000"; else fs<=fs+1; end if; end if; end process; fclk<=fs(3); process(fclk) begin if(fclk'event and fclk='1') then if(cc=29) then cc<="00000"; else cc<=cc+1; end if; end if; end process; cclk<=cc(4); process(cclk) begin if(cclk'event and cclk='1') then if(ll=481) then ll<="000000000"; else ll<=ll+1; end if; end if; end process; process(Clk) begin if(Clk'event and Clk='1') then if(cc>23) then HS<='0'; --horizontal synchronization else HS<='1'; end if; if(ll>479) then VS<='0'; --vertical synchronization else VS<='1'; end if; end if; end process; process(Clk) begin if(Clk'event and Clk='1') then if(cc<3) then grbx<="111"; elsif(cc<6) then grbx<="110"; elsif(cc<9) then grbx<="101"; elsif(cc<12) then grbx<="100"; elsif(cc<15) then grbx<="011"; elsif(cc<18) then grbx<="010"; elsif(cc<21) then grbx<="001"; else grbx<="000"; end if; end if; end process; process(Clk) begin if(Clk'event and Clk='1') then if(ll<60) then grby<="111"; elsif(ll<120) then grby<="110"; elsif(ll<180) then grby<="101"; elsif(ll<240) then grby<="100"; elsif(ll<300) then grby<="011"; elsif(ll<360) then grby<="010"; elsif(ll<420) then grby<="001"; else grby<="000"; end if; end if; end process; end behave;