INTEGRATED CIRCUITS
Philips
Semiconductors
PHILIPS
1999 Jun 17
P89C51RC+/RD+
P89C51Uxxx/52Uxxx
P89C54Uxxx/58Uxxx
Flash Memory
Microcontrollers
Program/Erase
Specifications
1999 Jun 17 2
P89C51RX+
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with FLASH EPROM program memory
DIP - Package outlines SOT129-1; PLCC - Package outlines SOT187-2; QFP - Package outlines SOT307-2
DIP PLCC QFP PIN NAME
NAME DURING
PROGRAMMING.
I/O
FUNCTION DURING
PROGRAMMING
- 1 39 N.C.
1 2 40 P1.0 A0 I Address input
2 3 41 P1.1 A1 I Address input
3 4 42 P1.2 A2 I Address input
4 5 43 P1.3 A3 I Address input
5 6 44 P1.4 A4 I Address input
6 7 1 P1.5 A5 I Address input
7 8 2 P1.6 A6 I Address input
8 9 3 P1.7 A7 I Address input
9 10 4 RST RST=1 I Reset always connected to High
10 11 5 P3.0 MODE0 Mode select
- 12 6 N.C.
11 13 7 P3.1 MODE1 Mode select
12 14 8 P3.2
13 15 9 P3.3 CE Chip Select
14 16 10 P3.4 A14 I Address input
15 17 11 P3.5 A15 I Address input
16 18 12 P3.6 P3.6 I Mode select
17 19 13 P3.7 MODE2 I Mode select
18 20 14 XTAL2 XTAL2 O Clock out
19 21 15 XTAL1 XTAL1 I Clock in
20 22 16 V
SS
V
SS
P Ground
- 23 17 N.C.
21 24 18 P2.0 A8 I Address input
22 25 19 P2.1 A9 I Address input
23 26 20 P2.2 A10 I Address input
24 27 21 P2.3 A11 I Address input
25 28 22 P2.4 A12 I Address input
26 29 23 P2.5 A13 I Address input
27 30 24 P2.6 MODE3 I Mode select
28 31 25 P2.7 OE I Output Enable
29 32 26 PSEN PSEN=0 I PSEN always connected to Low
30 33 27 ALE WR I Write
- 34 28 N.C.
31 35 29 EA V
PP
/V
IH
12.25V or 5V
32 36 30 P0.7 D7 I/O Data
33 37 31 P0.6 D6 I/O Data
34 38 32 P0.5 D5 I/O Data
35 39 33 P0.4 D4 I/O Data
36 40 34 P0.3 D3 I/O Data
37 41 35 P0.2 D2 I/O Data
38 42 36 P0.1 D1 I/O Data
39 43 37 P0.0 D0 I/O Data
40 44 38 V
DD
V
DD
P +5V
1999 Jun 17 3
P89C51RX+
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with FLASH EPROM program memory
PROGRAMMING MODES
The Flash Microcontrollers have two programming modes:
a. Parallel programming on a programmer, like an EPROM Microcontroller
b. ISP - In System Programming - while the Microcontroller is soldered to the board.
The parallel programming is done on a programmer like an EPROM microcontroller. The parallel programming is
faster than the ISP programming and can be done even faster on a gang programmer with some Microcontrollers
programmed at the same time.
The ISP programming is done without removing the microcontroller from the system. The programming is done by
downloading the code into the microcontroller and calling non-erasable built-in subroutines in the Micro’s ROM area.
The user can download the code by using loader subroutines located in the ROM area, or use other loader routines
written by the user and located in the Flash area.
During the ISP programming, connect pin EA to programming voltage VPP=12.25V ± 0.25V
Programming areas in the FLASH microcontroller
The microcontroller has several programming areas. These areas are programmed by the manufacturer during
manufacturing, or by the user.
Table 1 Programming areas in the FLASH microcontroller
Note 1: The Boot Vector byte and the Status byte exist in the P89C51RX+ parts only.
The P89C51Uxxx/52Uxxx/54Uxxx/58Uxxx do not support ISP and do not have the Boot Vector byte and the Status byte.
The programmer should not have an option to read/change the boot vector and status byte for the P89C51Uxxx/52Uxxx/
54Uxxx/58Uxxx parts.
Boot ROM
The “Boot ROM” area is located at address FC00H-FFFFH in a non erasable masked ROM. The boot ROM area
contains the following code:
a. Serial communication code to talk to a PC during the ISP programming.
b. Program/Erase/Verify subroutines used during the ISP programming.
The Boot ROM overlays the program flash memory space at the top 1k addresses, from FC00H to FFFFH. The Boot
ROM may be turned off by SFR AUXR1 bit 5, and the upper 1k bytes of FLASH memory is accessible by the user.
Not erasable/
Non
programmable
Boot ROM
Manufacturer’s
Programming
Parallel
programming
ISP
programming
Boot ROM at address FC00H-FFFFH Mask ROM
Boot Vector byte (note 1) X X X
Status byte (note 1) X X X
Manufacturer’s three ID signature bytes X
Three LOCK bits X X X
Flash memory at address 0 - FFFFH X X X
1999 Jun 17 4
P89C51RX+
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with FLASH EPROM program memory
Status byte and Boot vector byte
The Status byte and the Boot vector byte are located in the programmable flash memory.
After RESET the Microcontrollers HW checks the status byte:
a. If STATUS BYTE = 0; the program begins executing from address 0 of the FLASH memory.
b. If STATUS BYTE > 0; the program jumps to the address pointed by the “Boot Vector” byte. The pointed address
is the beginning of the ISP code. The ISP code always begins at a 256 byte boundary; the Boot Vector byte points
to the MSB byte of the address.
After programming the FLASH memory, the status byte should be programmed to 0 in order to allow
execution of the user’s code beginning at address 0. Programming the SB to 0 should be done for the
89C51RX+ and for the P89C5xU parts as well.
The user has three ways to jump to the ISP program:
a. Call the ISP program from the user’s application.
b. Write Status Byte > 0; the program will jump to the ISP program after reset.
c. Force the program to jump to the “boot vector” address by pulling:
PSEN = LOW
EA = +12.25V
ALE = High or left not connected
RESET = HIGH
The program will jump to the ISP program at the falling edge of RESET.
Note: The Boot Vector byte and the Status byte exist in the P89C51RX+ parts only.
The P89C51Uxxx/52Uxxx/54Uxxx/58Uxxx do not support ISP and do not have the Boot Vector byte and the Status byte.
Boot Vector byte
After RESET the program jumps to the address pointed by the “Boot Vector” byte. The “boot vector” is one byte only
and points to bytes located on 256 byte boundaries. The ISP program is usually located at address FC00H, and the
“boot vector” byte contains “FCH”. Do not change this unless an ISP program is located elsewhere. An ISP program
can be at any location in the 64K, the program should begin at a 256 byte boundary.
We recommend users to have a fault tolerant ISP programming by using the following sequence:
1. Program the Boot Vector byte to point to the ISP fault recovery code. Address FCH if using the default serial
loader.
2. Program the status byte to non-zero value (FFH is preferred).
3. Do the ISP programming.
4. Erase both status byte and boot vector after ISP has been successfully done. There is no way to erase the status
byte without the Boot Vector byte.
5. Program boot vector back to the original value(FCH) if user want to keep the default serial loader as the ISP
communication channel after ISP is done.
6. Write 00H to the Status Byte; the program will begin at address 0 after master reset.
1999 Jun 17 5
P89C51RX+
Philips Semiconductors
CMOS single-chip 8-bit microcontroller
with FLASH EPROM program memory
Flash memory map
Figure 1: Flash memory map
Figure 2: Checking the Status Byte after Master Reset
64K
63K
0
BOOT ROM
8K
16K
32K
48K
FLASHROM
ISP CODE
Block 0
Block 1
Block 2
Block 3
Block 4
P89C51RB+
P89C51RC+
P89C51RD+
P89C54U
P89C51RA+
P89C51U, P89C52U
P89C58U
64K
63K
0
BOOT VECTOR
BYTE = 0
RESET
YES
NO
GO TO ADDRESS 0
BOOT ROM
8K
16K
32K
48K
FLASH
ROM
PSEN = LOW
ALE = EA = HIGH
ISP CODE
STATUS
FORCE
ISP
at RESET falling
Block 0
Block 1
Block 2
Block 3
Block 4
edge
YES
NO
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