single_step.rar_stepping

/* * A code-rewriter that enables instruction single-stepping. */ #include <linux/smp.h> #include <linux/ptrace.h> #include <linux/slab.h> #include <linux/thread_info.h> #include <linux/uaccess.h> #include <linux/mman.h> #include <linux/types.h> #include <linux/err.h> #include <linux/prctl.h> #include <asm/cacheflush.h> #include <asm/traps.h> #include <asm/uaccess.h> #include <asm/unaligned.h> #include <arch/abi.h> #include <arch/spr_def.h> #include <arch/opcode.h> #ifndef __tilegx__ /* Hardware support for single step unavailable. */ #define signExtend17(val) sign_extend((val), 17) #define TILE_X1_MASK (0xffffffffULL << 31) enum mem_op { MEMOP_NONE, MEMOP_LOAD, MEMOP_STORE, MEMOP_LOAD_POSTINCR, MEMOP_STORE_POSTINCR }; static inline tilepro_bundle_bits set_BrOff_X1(tilepro_bundle_bits n, s32 offset) { tilepro_bundle_bits result; /* mask out the old offset */ tilepro_bundle_bits mask = create_BrOff_X1(-1); result = n & (~mask); /* or in the new offset */ result |= create_BrOff_X1(offset); return result; } static inline tilepro_bundle_bits move_X1(tilepro_bundle_bits n, int dest, int src) { tilepro_bundle_bits result; tilepro_bundle_bits op; result = n & (~TILE_X1_MASK); op = create_Opcode_X1(SPECIAL_0_OPCODE_X1) | create_RRROpcodeExtension_X1(OR_SPECIAL_0_OPCODE_X1) | create_Dest_X1(dest) | create_SrcB_X1(TREG_ZERO) | create_SrcA_X1(src) ; result |= op; return result; } static inline tilepro_bundle_bits nop_X1(tilepro_bundle_bits n) { return move_X1(n, TREG_ZERO, TREG_ZERO); } static inline tilepro_bundle_bits addi_X1( tilepro_bundle_bits n, int dest, int src, int imm) { n &= ~TILE_X1_MASK; n |= (create_SrcA_X1(src) | create_Dest_X1(dest) | create_Imm8_X1(imm) | create_S_X1(0) | create_Opcode_X1(IMM_0_OPCODE_X1) | create_ImmOpcodeExtension_X1(ADDI_IMM_0_OPCODE_X1)); return n; } static tilepro_bundle_bits rewrite_load_store_unaligned( struct single_step_state *state, tilepro_bundle_bits bundle, struct pt_regs *regs, enum mem_op mem_op, int size, int sign_ext) { unsigned char __user *addr; int val_reg, addr_reg, err, val; int align_ctl; align_ctl = unaligned_fixup; switch (task_thread_info(current)->align_ctl) { case PR_UNALIGN_NOPRINT: align_ctl = 1; break; case PR_UNALIGN_SIGBUS: align_ctl = 0; break; } /* Get address and value registers */ if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) { addr_reg = get_SrcA_Y2(bundle); val_reg = get_SrcBDest_Y2(bundle); } else if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) { addr_reg = get_SrcA_X1(bundle); val_reg = get_Dest_X1(bundle); } else { addr_reg = get_SrcA_X1(bundle); val_reg = get_SrcB_X1(bundle); } /* * If registers are not GPRs, don't try to handle it. * * FIXME: we could handle non-GPR loads by getting the real value * from memory, writing it to the single step buffer, using a * temp_reg to hold a pointer to that memory, then executing that * instruction and resetting temp_reg. For non-GPR stores, it's a * little trickier; we could use the single step buffer for that * too, but we'd have to add some more state bits so that we could * call back in here to copy that value to the real target. For * now, we just handle the simple case. */ if ((val_reg >= PTREGS_NR_GPRS && (val_reg != TREG_ZERO || mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR)) || addr_reg >= PTREGS_NR_GPRS) return bundle; /* If it's aligned, don't handle it specially */ addr = (void __user *)regs->regs[addr_reg]; if (((unsigned long)addr % size) == 0) return bundle; /* * Return SIGBUS with the unaligned address, if requested. * Note that we return SIGBUS even for completely invalid addresses * as long as they are in fact unaligned; this matches what the * tilepro hardware would be doing, if it could provide us with the * actual bad address in an SPR, which it doesn't. */ if (align_ctl == 0) { siginfo_t info = { .si_signo = SIGBUS, .si_code = BUS_ADRALN, .si_addr = addr }; trace_unhandled_signal("unaligned trap", regs, (unsigned long)addr, SIGBUS); force_sig_info(info.si_signo, &info, current); return (tilepro_bundle_bits) 0; } /* Handle unaligned load/store */ if (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) { unsigned short val_16; switch (size) { case 2: err = copy_from_user(&val_16, addr, sizeof(val_16)); val = sign_ext ? ((short)val_16) : val_16; break; case 4: err = copy_from_user(&val, addr, sizeof(val)); break; default: BUG(); } if (err == 0) { state->update_reg = val_reg; state->update_value = val; state->update = 1; } } else { unsigned short val_16; val = (val_reg == TREG_ZERO) ? 0 : regs->regs[val_reg]; switch (size) { case 2: val_16 = val; err = copy_to_user(addr, &val_16, sizeof(val_16)); break; case 4: err = copy_to_user(addr, &val, sizeof(val)); break; default: BUG(); } } if (err) { siginfo_t info = { .si_signo = SIGBUS, .si_code = BUS_ADRALN, .si_addr = addr }; trace_unhandled_signal("bad address for unaligned fixup", regs, (unsigned long)addr, SIGBUS); force_sig_info(info.si_signo, &info, current); return (tilepro_bundle_bits) 0; } if (unaligned_printk || unaligned_fixup_count == 0) { pr_info("Process %d/%s: PC %#lx: Fixup of" " unaligned %s at %#lx.\n", current->pid, current->comm, regs->pc, (mem_op == MEMOP_LOAD || mem_op == MEMOP_LOAD_POSTINCR) ? "load" : "store", (unsigned long)addr); if (!unaligned_printk) { #define P pr_info P("\n"); P("Unaligned fixups in the kernel will slow your application considerably.\n"); P("To find them, write a \"1\" to /proc/sys/tile/unaligned_fixup/printk,\n"); P("which requests the kernel show all unaligned fixups, or write a \"0\"\n"); P("to /proc/sys/tile/unaligned_fixup/enabled, in which case each unaligned\n"); P("access will become a SIGBUS you can debug. No further warnings will be\n"); P("shown so as to avoid additional slowdown, but you can track the number\n"); P("of fixups performed via /proc/sys/tile/unaligned_fixup/count.\n"); P("Use the tile-addr2line command (see \"info addr2line\") to decode PCs.\n"); P("\n"); #undef P } } ++unaligned_fixup_count; if (bundle & TILEPRO_BUNDLE_Y_ENCODING_MASK) { /* Convert the Y2 instruction to a prefetch. */ bundle &= ~(create_SrcBDest_Y2(-1) | create_Opcode_Y2(-1)); bundle |= (create_SrcBDest_Y2(TREG_ZERO) | create_Opcode_Y2(LW_OPCODE_Y2)); /* Replace the load postincr with an addi */ } else if (mem_op == MEMOP_LOAD_POSTINCR) { bundle = addi_X1(bundle, addr_reg, addr_reg, get_Imm8_X1(bundle)); /* Replace the store postincr with an addi */ } else if (mem_op == MEMOP_STORE_POSTINCR) { bundle = addi_X1(bundle, addr_reg, addr_reg, get_Dest_Imm8_X1(bundle)); } else { /* Convert the X1 instruction to a nop. */ bundle &= ~(create_Opcode_X1(-1) | create_UnShOpcodeExtension_X1(-1) | create_UnOpcodeExtension_X1(-1)); bundle |= (create_Opcode_X1(SHUN_0_OPCODE_X1) | create_UnShOpcodeExtension_X1( UN_0_SHUN_0_OPCODE_X1) | create_UnOpcodeExtension_X1( NOP_UN_0_SHUN_0_OPCODE_X1)); } return bundle; } /* * Called after execve() has started the new image. This allows us * to reset the info state. Note that the the mmap'ed memory, if there * was any, has already been unmapped by the exec. */ void single_step_execve(void) { struct thread_info *ti = current_thread_info(); kfree(ti->step_state); ti->step_state = NULL; } /* * single_step_once() - entry point when single stepping has been triggered. * @regs: The machine register state * * When we arrive at this routine via a trampoline, the single step * engine copies the executing bundle to the single step buffer. * If the instruction is a condition branch, then the target is * reset to one past th