LatticeMico32 Processor
Reference Manual
Lattice Semiconductor Corporation
5555 NE Moore Court
Hillsboro, OR 97124
(503) 268-8000
July 2009
LatticeMico32 Processor Reference Manual ii
Copyright
Copyright © 2008 Lattice Semiconductor Corporation.
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(logo), L (stylized), L (design), Lattice (design), LSC, E
2
CMOS, Extreme
Performance, FlashBAK, flexiFlash, flexiMAC, flexiPCS, FreedomChip, GAL,
GDX, Generic Array Logic, HDL Explorer, IPexpress, ISP, ispATE, ispClock,
ispDOWNLOAD, ispGAL, ispGDS, ispGDX, ispGDXV, ispGDX2,
ispGENERATOR, ispJTAG, ispLEVER, ispLeverCORE, ispLSI, ispMACH,
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ispXPGA, ispXPLD, LatticeEC, LatticeECP, LatticeECP-DSP, LatticeECP2,
LatticeECP2M, LatticeMico8, LatticeMico32, LatticeSC, LatticeSCM,
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Simple Machine for Complex Design, TransFR, UltraMOS, and specific
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Other product names used in this publication are for identification purposes
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LatticeMico32 Processor Reference Manual iii
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Convention Meaning or Use
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Ctrl+L Press the two keys at the same time.
Courier Code examples. Messages, reports, and prompts from the software.
...
Omitted material in a line of code.
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Omitted lines in code and report examples.
[ ]
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LatticeMico32 Processor Reference Manual iv
LatticeMico32 Processor Reference Manual v
Contents
Chapter 1 LatticeMico32 Processor and Systems 1
Chapter 2 Programmer’s Model 5
Pipeline Architecture 5
Data Types 6
Register Architecture 7
General-Purpose Registers 7
Control and Status Registers 9
Memory Architecture 14
Address Space 14
Endianness 14
Address Alignment 15
Stack Layout 15
Caches 16
Inline Memories 18
Exceptions 20
Exception Processing 21
Exception Handlers 22
Nested Exceptions 26
Remapping the Exception Table 26
Reset Summary 26
Using Breakpoints 27
Using Watchpoints 27
Debug Architecture 28
DC – Debug Control 29
DEBA – Debug Exception Base Address 29
JTX – JTAG UART Transmit Register 29
JRX – JTAG UART Receive Register 30
BPn – Breakpoint 30
WPn – Watchpoint 31
Instruction Set Categories 31