CAN，FPGA与SJA1000通信.rar_can 总线_can接收_checkwm5_fpga can_sja1000 fp

TABLE OF CONTENTS 1) Peripheral Summary 2) Description of Generated Files 3) Description of Used IPIC Signals 4) Description of Top Level Generics ================================================================================ * 1) Peripheral Summary * ================================================================================ Peripheral Summary: XPS project / EDK repository : D:\edk_prj logical library name : can_shy_v1_00_a top name : can_shy version : 1.00.a type : PLB (v4.6) slave features : slave attachment soft reset interrupt control user s/w registers Address Block for User Logic and IPIF Predefined Services user logic slave space : C_BASEADDR + 0x00000000 : C_BASEADDR + 0x000000FF software reset space : C_BASEADDR + 0x00000100 : C_BASEADDR + 0x000001FF interrupt control space : C_BASEADDR + 0x00000200 : C_BASEADDR + 0x000002FF ================================================================================ * 2) Description of Generated Files * ================================================================================ - HDL source file(s) hdl/vhdl/can_shy.vhd This is the template file for your peripheral's top design entity. It configures and instantiates the corresponding design units in the way you indicated in the wizard GUI and hooks it up to the stub user logic where the actual functionalites should get implemented. You are not expected to modify this template file except certain marked places for adding user specific generics and ports. vhdl/user_logic.vhd This is the template file for the stub user logic design entity, either in VHDL or Verilog, where the actual functionalities should get implemented. Some sample code snippet may be provided for demonstration purpose. - XPS interface file(s) data/can_shy_v2_1_0.mpd This Microprocessor Peripheral Description file contains information of the interface of your peripheral, so that other EDK tools can recognize your peripheral. data/can_shy_v2_1_0.pao This Peripheral Analysis Order file defines the analysis order of all the HDL source files that are used to compile your peripheral. - ISE project file(s) devl/projnav/can_shy.ise This is the ProjNavigator project file. It sets up the needed logical libraries and dependent library files for you to help you develop your peripheral using ProjNavigator. devl/projnav/can_shy.cli This is the TCL command line file used to generate the .ise file. - XST synthesis file(s) devl/synthesis/can_shy_xst.scr This is the XST synthesis script file to compile your peripheral. Note: you may want to modify the device part option for your target. devl/synthesis/can_shy_xst.prj This is the XST synthesis project file used by the above script file to compile your peripheral. - Driver source file(s) src/can_shy.h This is the software driver header template file, which contains address offset of software addressable registers in your peripheral, as well as some common masks and simple register access macros or function declaration. src/can_shy.c This is the software driver source template file, to define all applicable driver functions. src/can_shy_selftest.c This is the software driver self test example file, which contain self test example code to test various hardware features of your peripheral. src/Makefile This is the software driver makefile to compile drivers. - Driver interface file(s) -user needs to add these to repositories path in SDK (Xilinx Tools-->Repositories) data/can_shy_v2_1_0.mdd This is the Microprocessor Driver Definition file. data/can_shy_v2_1_0.tcl This is the Microprocessor Driver Command file. - Other misc file(s) devl/ipwiz.opt This is the option setting file for the wizard batch mode, which should generate the same result as the wizard GUI mode. devl/README.txt This README file for your peripheral. devl/ipwiz.log This is the log file by operating on this wizard. ================================================================================ * 3) Description of Used IPIC Signals * ================================================================================ For more information (usage, timing diagrams, etc.) regarding the IPIC signals used in the templates, please refer to the following specifications: proc_common_v3_00_a No documentation for this library plbv46_slave_single_v1_01_a D:\edk_prj\D:\jobtools\xilinx14.1\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_single_v1_01_a\doc\plbv46_slave_single.pdf interrupt_control_v2_01_a D:\edk_prj\D:\jobtools\xilinx14.1\14.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\doc\interrupt_control.pdf Bus2IP_Clk Synchronization clock provided to the user logic. All IPIC signals are synchronous to this clock. It is identical to the input <bus>_Clk signal of the peripheral. No additional buffering is provided on the clock; it is passed through as is. Bus2IP_Reset Active high reset used by the user logic. It is asserted whenever the <bus>_Rst signal asserts or whenever there is a software-programmed reset (if the soft reset block is included). Bus2IP_CS Active high chip select bus. Assertion of a chip select indicates an active transaction request to the chip select's target address space. This is typically used for user logic memory space selection. Bus2IP_Data Write data bus to the user logic. Write data is accepted by the user logic during a write operation by assertion of the write acknowledgement signal and the rising edge of the Bus2IP_Clk. Bus2IP_BE Byte Enable qualifiers for the requested read or write operation to the user logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates that byte lanes 2 and 3 contain valid data. Bus2IP_RdCE Active high chip enable bus to the user logic. These chip enables are only asserted during active read transaction requests with the target address space and in conjunction with the corresponding sub-address within the space. These are typically used for user logic readable registers selection. Bus2IP_WrCE Active high chip enable bus to the user logic. These chip enables are asserted only during active write transaction requests with the target address space and in conjunction with the corresponding sub-address within the space. Typically used for user logic writable registers selection. IP2Bus_Data Output read data bus from the user logic; data is qualified with the assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk. IP2Bus_RdAck Active high read data qualifier providing the read acknowledgement from the user logic. Read data on the IP2Bus_Data bus is deemed valid at the rising edge of the Bus2IP_Clk and IP2Bus_RdAck asserted high by the user logic. IP2Bus_Wr