Release 9.1i - par J.30
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
Tue Feb 21 09:57:05 2012
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: FPGA_SDRAM_map.ncd
OUTPUT FILE: FPGA_SDRAM_pad.txt
PART TYPE: xc4vlx15
SPEED GRADE: -12
PACKAGE: sf363
Pinout by Pin Number:
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|A2 | | |GND | | | | | | | | | | | | |
|A3 | |IOBM |IO_L6P_6 |UNUSED | |6 | | | | | | | | | |
|A4 | | |VCCO_6 | | |6 | | | | |any******| | | | |
|A5 | |IOBM |IO_L2P_6 |UNUSED | |6 | | | | | | | | | |
|A6 | |IOBS |IO_L1N_6 |UNUSED | |6 | | | | | | | | | |
|A7 |CLK50 |IOB |IO_L8P_GC_LC_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|A8 |CLK100 |IOB |IO_L6P_GC_LC_3 |INPUT |LVCMOS25 |3 | | | |NONE | |LOCATED | |NO |NONE |
|A9 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|A10 | |LOWCAPIOB|IO_L2P_GC_VRN_LC_3 |UNUSED | |3 | | | | | | | | | |
|A11 | |LOWCAPIOB|IO_L1N_GC_CC_LC_3 |UNUSED | |3 | | | | | | | | | |
|A12 | | |VCCO_3 | | |3 | | | | |2.50 | | | | |
|A13 | |LOWCAPIOB|IO_L5N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|A14 | |LOWCAPIOB|IO_L7N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|A15 | |IOBS |IO_L1N_5 |UNUSED | |5 | | | | | | | | | |
|A16 | |IOBM |IO_L2P_5 |UNUSED | |5 | | | | | | | | | |
|A17 | | |VCCO_5 | | |5 | | | | |2.50 | | | | |
|A18 | |IOBM |IO_L6P_5 |UNUSED | |5 | | | | | | | | | |
|A19 | | |GND | | | | | | | | | | | | |
|A20 | | |GND | | | | | | | | | | | | |
|B1 | | |GND | | | | | | | | | | | | |
|B2 | |LOWCAPIOB|IO_L8P_CC_LC_6 |UNUSED | |6 | | | | | | | | | |
|B3 | |IOBS |IO_L6N_6 |UNUSED | |6 | | | | | | | | | |
|B4 | |IOBM |IO_L4P_6 |UNUSED | |6 | | | | | | | | | |
|B5 | |IOBS |IO_L2N_6 |UNUSED | |6 | | | | | | | | | |
|B6 | |IOBM |IO_L1P_6 |UNUSED | |6 | | | | | | | | | |
|B7 | |LOWCAPIOB|IO_L8N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B8 | |LOWCAPIOB|IO_L6N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B9 | |LOWCAPIOB|IO_L2N_GC_VRP_LC_3 |UNUSED | |3 | | | | | | | | | |
|B10 | |LOWCAPIOB|IO_L4P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B11 | |LOWCAPIOB|IO_L3N_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B12 | |LOWCAPIOB|IO_L1P_GC_CC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B13 | |LOWCAPIOB|IO_L5P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B14 | |LOWCAPIOB|IO_L7P_GC_LC_3 |UNUSED | |3 | | | | | | | | | |
|B15 | |IOBM |IO_L1P_5 |UNUSED | |5 |
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SDRAM.zip_vhdl dram
共232个文件
vho:34个
dat:18个
obj:18个
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在ISE环境下对SDRAM(异步动态存储器)的控制模块设计。
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SDRAM.zip_vhdl dram (232个子文件)
_1 26KB
_info 5KB
test.ant 12KB
sdr.ant 12KB
testbench_arch.asm 36KB
behavioral.asm 36KB
testbench_arch.asm 35KB
rtl.asm 26KB
rtl.asm 16KB
rtl.asm 10KB
behavioral.asm 9KB
behavioral.asm 6KB
rtl.asm 4KB
fpga_sdram.bgn 7KB
fpga_sdram.bit 582KB
FPGA_SDRAM_cs.blc 680B
FPGA_SDRAM.bld 1KB
test_sdr.cdc 6KB
FPGA_SDRAM.cel 0B
_impact.cmd 487B
isim.cmd 10B
FPGA_SDRAM.cmd_log 59KB
123.cpj 28KB
xsimtestbench_arch.cpp 2KB
xsimtestbench_arch.cpp 2KB
FPGA_SDRAM_pad.csv 16KB
testbench_arch.dat 8KB
testbench_arch.dat 7KB
behavioral.dat 6KB
rtl.dat 4KB
rtl.dat 3KB
behavioral.dat 3KB
rtl.dat 2KB
behavioral.dat 1KB
_primary.dat 879B
_primary.dat 848B
_primary.dat 806B
_primary.dat 630B
rtl.dat 408B
_primary.dat 402B
_primary.dat 339B
_primary.dat 307B
_primary.dat 231B
_primary.dat 230B
fpga_sdram.drc 450B
ila_pro_0.edn 1.45MB
icon_pro.edn 104KB
test_isim_beh.exe 2MB
sdr_isim_beh.exe 1.99MB
test.fdo 541B
sdr.fdo 538B
vpkg.h 7KB
dcm_adv_v.h 1KB
dcm_adv_maximum_period_check_v.h 1KB
dcm_adv_clock_divide_by_2_v.h 1KB
vcomponents.h 1KB
dcm_adv_clock_lost_v.h 1KB
behavioral.h 1KB
testbench_arch.h 1KB
testbench_arch.h 1KB
rtl.h 1024B
behavioral.h 1000B
rtl.h 999B
behavioral.h 992B
rtl.h 991B
behavioral.h 990B
ibufg_v.h 980B
rtl.h 978B
bufg_v.h 947B
isim.hdlsourcefiles 316B
device_usage_statistics.html 116KB
FPGA_SDRAM_summary.html 8KB
xilinxsim.ini 16B
SDRAM.ipf 3KB
SDRAM.ipf_ISE_Backup 3KB
SDRAM.ise 348KB
SDRAM.ise_ISE_Backup 348KB
test_sdr.jhd 53B
test.jhd 49B
sdr.jhd 48B
FPGA_SDRAM.lfp 149B
_impact.log 4KB
isim.log 1KB
xaw2vhdl.log 34B
FPGA_SDRAM.lso 6B
netlist.lst 55B
FPGA_SDRAM_map.map 3KB
FPGA_SDRAM_map.mrp 30KB
fpga_sdram.msd 4.79MB
fpga_sdram.msk 582KB
FPGA_SDRAM_last_par.ncd 492KB
FPGA_SDRAM_guide.ncd 422KB
FPGA_SDRAM.ncd 422KB
FPGA_SDRAM_map.ncd 206KB
icon_pro.ncf 392B
ila_pro_0.ncf 253B
FPGA_SDRAM_cs.ngc 651KB
FPGA_SDRAM.ngc 149KB
FPGA_SDRAM_prev_built.ngd 1.13MB
FPGA_SDRAM.ngd 1.13MB
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