TAMPERE UNIVERSITY OF TECHNOLOGY
Department of Electrical Engineering
JAAKKO SERTAMO
PROCESSOR GENERATOR FOR TRANSPORT TRIGGERED
ARCHITECTURES
Master of Science Thesis
Subject approved by Department Council
20th Aug, 2003
Examiners: Prof. Jarmo Takala
Prof. Markku Kivikoski
PREFACE
The work for this thesis was carried out in Institute of Digital and Computer Systems of
Tampere University of Technology in 2002-2003 as a part of the Flexible Design Met-
hods for DSP Systems (FlexDSP) project funded by the National Technology Agency.
I would like to express my sincere gratitude to my thesis supervisor Professor Jarmo
Takala for his guidance and valuable tips for the thesis.
I would also like to thank my workmates at institute of digital and computer systems for
their company and assistance during the last two and half years I have been working at
the institute.
Finally, I wish to thank my parents for their support throughout my studies.
Tampere, September 15, 2003
Jaakko Sertamo
Männikönkatu 3 A 12
33820 Tampere
p. 040 5937266
jaakko.sertamo@tut.fi
TABLE OF CONTENTS
Abstract
4
Tiivistelmä
6
List of Abbreviations and Symbols
9
1. Introduction
11
2. Transport Triggered Architectures
14
2.1 From VLIW to TTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Hardware Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Interconnection Network . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Transport Pipelining . . . . . . . . . . . . . . . . . . . . . . . 18
2.2.3 Functional Units and Register Files . . . . . . . . . . . . . . . 18
2.3 Software Aspects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.4 Realizations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.4.1 32-bit General-Purpose Processor . . . . . . . . . . . . . . . . 22
2.4.2 Application-Specific Processor for Navigation Receiver . . . . 24
3. MOVE Framework
26
3.1 Architecture Template . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Design Space Explorer . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.2.1 Resource Optimization . . . . . . . . . . . . . . . . . . . . . . 30
3.2.2 Connectivity Optimization . . . . . . . . . . . . . . . . . . . . 30
3.3 Software Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.4 Hardware Subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table of Contents
3
3.4.1 MOVE Estimator . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4.2 MOVE Processor Generator . . . . . . . . . . . . . . . . . . . 33
4. New Processor Generator
37
4.1 Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
4.1.1 General Requirements . . . . . . . . . . . . . . . . . . . . . . 37
4.1.2 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
4.1.3 Modularity . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
4.1.4 Support for Different Interconnection Structures . . . . . . . . 40
4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
4.2.1 Processor Organization . . . . . . . . . . . . . . . . . . . . . . 42
4.2.2 Interconnection Network . . . . . . . . . . . . . . . . . . . . . 46
4.2.3 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
4.3 Functional Unit Library . . . . . . . . . . . . . . . . . . . . . . . . . . 52
5. Implementation Experiments
56
5.1 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.1.1 Full Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.1.2 Optimized Connectivity . . . . . . . . . . . . . . . . . . . . . 61
5.2 Clock Gating Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.3 Bus Structure Comparison . . . . . . . . . . . . . . . . . . . . . . . . 64
5.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6. Conclusions
69
Bibliography
71
Appendix A Functional Unit Template
Appendix B Register File
ABSTRACT
TAMPERE UNIVERSITY OF TECHNOLOGY
Degree Program in Electrical Engineering
Institute of Digital and Computer Systems
Sertamo, Jaakko Ilmari: Processor Generator for Transport Triggered Architectures
Master of Science Thesis: 73 pages, 5 appendix pages
Examiners: Prof. Jarmo Takala and Prof. Markku Kivikoski
Funding: The National Technology Agency
Department of Electrical Engineering
October 2003
Keywords: transport triggered architecture, electronic design automation
Application-specific instruction set processors can be used as building blocks of mo-
dern system-on-chips, increasing the design flexibility with programmability. Compared
to fixed-processor cores, instruction-set optimized processors also provide significantly
increased computational performance and energy efficiency. A wide range of architec-
tural, software and implementation skills are necessary in the design of an application-
specific CPU. The MOVE framework, a set of non-commercial software tools provide
a design environment for fast semi-automatic design of custom processors. The MOVE
framework consists of three components. Design space explorer automates the search
of the optimal configuration of the processor for a given application. Hardware subsys-
tem is responsible for estimating the cost of the processor configuration and generating
hardware description language representation of the processor design. Software subsys-
tem compiles high-level language application code to binary executables.
The MOVE framework utilizes the transport triggered architecture (TTA) as a proces-
sor template. TTA is VLIW-like instruction level parallelism processor architecture in
which data transports between function units and register files are programmed explicit-
ly instead of programming operations. Operations occur a as side effect of these explicit
transports. Transport triggered architecture is simple, extremely scalable and flexible
and therefore it is an attractive choice for embedded processors.
In this thesis, a processor generator for the MOVE framework that translates the high-
level structural information of a target TTA processor into register transfer level VHDL
description was designed. The designed processor generator improved the usability and
reliability of the of original processor generator of the MOVE framework as the desc-
ription of the target processor is obtained from specification files common to the rest of
the tools of the MOVE framework. A clear interface specification and a functional unit
