at91sam9g25.zip_Ignore It!_at91

11032C–ATARM–25-Jan-13

Description

Based on the ARM926EJ-S™ core, the SAM9G25 is an embedded microprocessor

unit, running at 400 MHz and featuring connectivity peripherals, a high data bandwidth

architecture and a small footprint package option, making it an optimized solution for

industrial applications.

The multi-layer bus matrix is linked to 2 x 8 DMA channels as well as DMAs dedicated

to the communication and interface peripherals, ensuring uninterrupted data transfers

bank DDR2/LPDDR, SDRAM/LPSDRAM, static memories, as well as specific circuitry

for MLC/SLC NAND Flash with integrated ECC up to 24 bits.

The SAM9G25 is available in a 217-ball BGA package with 0.8 mm ball pitch, as well

ideally suited for space-constrained applications.

AT91SAM ARM-based Embbedded MPU

SAM9G25

DATASHEET

2

z 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory

Management Unit

z One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND

®

or serial DataFlash. Programmable order.

z One 32-Kbyte internal SRAM, single-cycle access at system speed

z High Bandwidth Multi-port DDR2 Controller

Interval Timer, Watchdog Timer and Real Time Clock

z Boot Mode Select Option, Remap Command

z Internal Low Power 32 kHz RC and Fast 12 MHz RC Oscillators

z Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator

z One PLL for the system and one PLL at 480 MHz optimized for USB High

Speed

z Twelve 32-bit-layer AHB Bus Matrix for large Bandwidth transfers

z Dual Peripheral Bridge with dedicated programmable clock for best

performance

z Two dual port 8-channel DMA Controllers

Optimization Capabilities

z ITU-R BT. 601/656 Image Sensor Interface

z USB Device High Speed, USB Host High Speed and USB Host Full

z One 10/100 Mbps Ethernet MAC Controller

z Two High Speed Memory Card Hosts

z Two Master/Slave Serial Peripheral Interface

z Two 3-channel 32-bit Timer/Counters

z One Synchronous Serial Controller

3

z I/O

z Four 32-bit Parallel Input/Output Controllers

z 105 Programmable I/O Lines Multiplexed with up to Three Peripheral I/Os

z Input Change Interrupt Capability on Each I/O Line, optional Schmitt trigger input

z Individually Programmable Open-drain, Pull-up and pull-down resistor, Synchronous Output

z Packages

z 217-ball BGA, pitch 0.8 mm

z 247-ball TFBGA, pitch 0.5 mm

z 247-ball VFBGA, pitch 0.5 mm

4

2. Block Diagram

5

3. Signal Description