/*
* MSM 7k/8k High speed uart driver
*
* Copyright (c) 2007-2011, Code Aurora Forum. All rights reserved.
* Copyright (c) 2008 Google Inc.
* Modified: Nick Pelly <npelly@google.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
* See the GNU General Public License for more details.
*
* Has optional support for uart power management independent of linux
* suspend/resume:
*
* RX wakeup.
* UART wakeup can be triggered by RX activity (using a wakeup GPIO on the
* UART RX pin). This should only be used if there is not a wakeup
* GPIO on the UART CTS, and the first RX byte is known (for example, with the
* Bluetooth Texas Instruments HCILL protocol), since the first RX byte will
* always be lost. RTS will be asserted even while the UART is off in this mode
* of operation. See msm_serial_hs_platform_data.rx_wakeup_irq.
*/
#include <linux/module.h>
#include <linux/serial.h>
#include <linux/serial_core.h>
#include <linux/tty.h>
#include <linux/tty_flip.h>
#include <linux/slab.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/kernel.h>
#include <linux/timer.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
#include <linux/atomic.h>
#include <asm/irq.h>
#include <mach/hardware.h>
#include <mach/dma.h>
#include <linux/platform_data/msm_serial_hs.h>
/* HSUART Registers */
#define UARTDM_MR1_ADDR 0x0
#define UARTDM_MR2_ADDR 0x4
/* Data Mover result codes */
#define RSLT_FIFO_CNTR_BMSK (0xE << 28)
#define RSLT_VLD BIT(1)
/* write only register */
#define UARTDM_CSR_ADDR 0x8
#define UARTDM_CSR_115200 0xFF
#define UARTDM_CSR_57600 0xEE
#define UARTDM_CSR_38400 0xDD
#define UARTDM_CSR_28800 0xCC
#define UARTDM_CSR_19200 0xBB
#define UARTDM_CSR_14400 0xAA
#define UARTDM_CSR_9600 0x99
#define UARTDM_CSR_7200 0x88
#define UARTDM_CSR_4800 0x77
#define UARTDM_CSR_3600 0x66
#define UARTDM_CSR_2400 0x55
#define UARTDM_CSR_1200 0x44
#define UARTDM_CSR_600 0x33
#define UARTDM_CSR_300 0x22
#define UARTDM_CSR_150 0x11
#define UARTDM_CSR_75 0x00
/* write only register */
#define UARTDM_TF_ADDR 0x70
#define UARTDM_TF2_ADDR 0x74
#define UARTDM_TF3_ADDR 0x78
#define UARTDM_TF4_ADDR 0x7C
/* write only register */
#define UARTDM_CR_ADDR 0x10
#define UARTDM_IMR_ADDR 0x14
#define UARTDM_IPR_ADDR 0x18
#define UARTDM_TFWR_ADDR 0x1c
#define UARTDM_RFWR_ADDR 0x20
#define UARTDM_HCR_ADDR 0x24
#define UARTDM_DMRX_ADDR 0x34
#define UARTDM_IRDA_ADDR 0x38
#define UARTDM_DMEN_ADDR 0x3c
/* UART_DM_NO_CHARS_FOR_TX */
#define UARTDM_NCF_TX_ADDR 0x40
#define UARTDM_BADR_ADDR 0x44
#define UARTDM_SIM_CFG_ADDR 0x80
/* Read Only register */
#define UARTDM_SR_ADDR 0x8
/* Read Only register */
#define UARTDM_RF_ADDR 0x70
#define UARTDM_RF2_ADDR 0x74
#define UARTDM_RF3_ADDR 0x78
#define UARTDM_RF4_ADDR 0x7C
/* Read Only register */
#define UARTDM_MISR_ADDR 0x10
/* Read Only register */
#define UARTDM_ISR_ADDR 0x14
#define UARTDM_RX_TOTAL_SNAP_ADDR 0x38
#define UARTDM_RXFS_ADDR 0x50
/* Register field Mask Mapping */
#define UARTDM_SR_PAR_FRAME_BMSK BIT(5)
#define UARTDM_SR_OVERRUN_BMSK BIT(4)
#define UARTDM_SR_TXEMT_BMSK BIT(3)
#define UARTDM_SR_TXRDY_BMSK BIT(2)
#define UARTDM_SR_RXRDY_BMSK BIT(0)
#define UARTDM_CR_TX_DISABLE_BMSK BIT(3)
#define UARTDM_CR_RX_DISABLE_BMSK BIT(1)
#define UARTDM_CR_TX_EN_BMSK BIT(2)
#define UARTDM_CR_RX_EN_BMSK BIT(0)
/* UARTDM_CR channel_comman bit value (register field is bits 8:4) */
#define RESET_RX 0x10
#define RESET_TX 0x20
#define RESET_ERROR_STATUS 0x30
#define RESET_BREAK_INT 0x40
#define START_BREAK 0x50
#define STOP_BREAK 0x60
#define RESET_CTS 0x70
#define RESET_STALE_INT 0x80
#define RFR_LOW 0xD0
#define RFR_HIGH 0xE0
#define CR_PROTECTION_EN 0x100
#define STALE_EVENT_ENABLE 0x500
#define STALE_EVENT_DISABLE 0x600
#define FORCE_STALE_EVENT 0x400
#define CLEAR_TX_READY 0x300
#define RESET_TX_ERROR 0x800
#define RESET_TX_DONE 0x810
#define UARTDM_MR1_AUTO_RFR_LEVEL1_BMSK 0xffffff00
#define UARTDM_MR1_AUTO_RFR_LEVEL0_BMSK 0x3f
#define UARTDM_MR1_CTS_CTL_BMSK 0x40
#define UARTDM_MR1_RX_RDY_CTL_BMSK 0x80
#define UARTDM_MR2_ERROR_MODE_BMSK 0x40
#define UARTDM_MR2_BITS_PER_CHAR_BMSK 0x30
/* bits per character configuration */
#define FIVE_BPC (0 << 4)
#define SIX_BPC (1 << 4)
#define SEVEN_BPC (2 << 4)
#define EIGHT_BPC (3 << 4)
#define UARTDM_MR2_STOP_BIT_LEN_BMSK 0xc
#define STOP_BIT_ONE (1 << 2)
#define STOP_BIT_TWO (3 << 2)
#define UARTDM_MR2_PARITY_MODE_BMSK 0x3
/* Parity configuration */
#define NO_PARITY 0x0
#define EVEN_PARITY 0x1
#define ODD_PARITY 0x2
#define SPACE_PARITY 0x3
#define UARTDM_IPR_STALE_TIMEOUT_MSB_BMSK 0xffffff80
#define UARTDM_IPR_STALE_LSB_BMSK 0x1f
/* These can be used for both ISR and IMR register */
#define UARTDM_ISR_TX_READY_BMSK BIT(7)
#define UARTDM_ISR_CURRENT_CTS_BMSK BIT(6)
#define UARTDM_ISR_DELTA_CTS_BMSK BIT(5)
#define UARTDM_ISR_RXLEV_BMSK BIT(4)
#define UARTDM_ISR_RXSTALE_BMSK BIT(3)
#define UARTDM_ISR_RXBREAK_BMSK BIT(2)
#define UARTDM_ISR_RXHUNT_BMSK BIT(1)
#define UARTDM_ISR_TXLEV_BMSK BIT(0)
/* Field definitions for UART_DM_DMEN*/
#define UARTDM_TX_DM_EN_BMSK 0x1
#define UARTDM_RX_DM_EN_BMSK 0x2
#define UART_FIFOSIZE 64
#define UARTCLK 7372800
/* Rx DMA request states */
enum flush_reason {
FLUSH_NONE,
FLUSH_DATA_READY,
FLUSH_DATA_INVALID, /* values after this indicate invalid data */
FLUSH_IGNORE = FLUSH_DATA_INVALID,
FLUSH_STOP,
FLUSH_SHUTDOWN,
};
/* UART clock states */
enum msm_hs_clk_states_e {
MSM_HS_CLK_PORT_OFF, /* port not in use */
MSM_HS_CLK_OFF, /* clock disabled */
MSM_HS_CLK_REQUEST_OFF, /* disable after TX and RX flushed */
MSM_HS_CLK_ON, /* clock enabled */
};
/* Track the forced RXSTALE flush during clock off sequence.
* These states are only valid during MSM_HS_CLK_REQUEST_OFF */
enum msm_hs_clk_req_off_state_e {
CLK_REQ_OFF_START,
CLK_REQ_OFF_RXSTALE_ISSUED,
CLK_REQ_OFF_FLUSH_ISSUED,
CLK_REQ_OFF_RXSTALE_FLUSHED,
};
/**
* struct msm_hs_tx
* @tx_ready_int_en: ok to dma more tx?
* @dma_in_flight: tx dma in progress
* @xfer: top level DMA command pointer structure
* @command_ptr: third level command struct pointer
* @command_ptr_ptr: second level command list struct pointer
* @mapped_cmd_ptr: DMA view of third level command struct
* @mapped_cmd_ptr_ptr: DMA view of second level command list struct
* @tx_count: number of bytes to transfer in DMA transfer
* @dma_base: DMA view of UART xmit buffer
*
* This structure describes a single Tx DMA transaction. MSM DMA
* commands have two levels of indirection. The top level command
* ptr points to a list of command ptr which in turn points to a
* single DMA 'command'. In our case each Tx transaction consists
* of a single second level pointer pointing to a 'box type' command.
*/
struct msm_hs_tx {
unsigned int tx_ready_int_en;
unsigned int dma_in_flight;
struct msm_dmov_cmd xfer;
dmov_box *command_ptr;
u32 *command_ptr_ptr;
dma_addr_t mapped_cmd_ptr;
dma_addr_t mapped_cmd_ptr_ptr;
int tx_count;
dma_addr_t dma_base;
};
/**
* struct msm_hs_rx
* @flush: Rx DMA request state
* @xfer: top level DMA command pointer structure
* @c
