FPGA-DDS.rar_DDS 直接数字频率合成

WHEN "1111110100"=>OUTP<="111101101";相位累加器SUM99的VHDL源程序 --SUM99.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY SUM99 IS PORT(K: IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK: IN STD_LOGIC; EN: IN STD_LOGIC; RESET: IN STD_LOGIC; OUT1: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END ENTITY SUM99; ARCHITECTURE ART OF SUM99 IS SIGNAL TEMP: STD_LOGIC_VECTOR(9 DOWNTO 0); BEGIN PROCESS(CLK, EN, RESET) IS BEGIN IF RESET='1'THEN TEMP<="0000000000"; ELSE IF CLK'EVENT AND CLK='1'THEN IF EN='1' THEN TEMP<=TEMP+K; END IF; END IF; END IF; OUT1<=TEMP; END PROCESS; END ARCHITECTURE ART; 2.4.2 相位寄存器REG1的VHDL源程序 --REG1.VHD (REG2.VHD与REG1.VHD相似) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY REG1 IS PORT(D: IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK: IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END ENTITY REG1; ARCHITECTURE ART OF REG1 IS BEGIN PROCESS(CLK) IS BEGIN IF(CLK'EVENT AND CLK='1')THEN Q<=D; END IF; END PROCESS; END ARCHITECTURE ART; 2.4.3 正弦查找表ROM的VHDL源程序 --ROM.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY ROM IS PORT (ADDR:IN STD_LOGIC_VECTOR (9 DOWNTO 0); CLK:IN STD_LOGIC; OUTP:OUT SIGNED (8 DOWNTO 0)); END ENTITY ROM; ARCHITECTURE ART OF ROM IS BEGIN PROCESS (CLK) IS BEGIN IF (CLK'EVENT AND CLK='1')THEN CASE ADDR IS WHEN "0000000000"=>OUTP<="000000000"; WHEN "0000000001"=>OUTP<="000000010"; WHEN "0000000010"=>OUTP<="000000011"; WHEN "0000000011"=>OUTP<="000000101"; WHEN "0000000100"=>OUTP<="000000110"; WHEN "0000000101"=>OUTP<="000001000"; WHEN "0000000110"=>OUTP<="000001001"; WHEN "0000000111"=>OUTP<="000001011"; WHEN "0000001000"=>OUTP<="000001101"; WHEN "0000001001"=>OUTP<="000001110"; WHEN "0000001010"=>OUTP<="000010000"; WHEN "1111101001"=>OUTP<="111011100"; WHEN "1111101010"=>OUTP<="111011110"; WHEN "1111101011"=>OUTP<="111011111"; WHEN "1111101100"=>OUTP<="111100001"; WHEN "1111101101"=>OUTP<="111100010"; WHEN "1111101110"=>OUTP<="111100100"; WHEN "1111101111"=>OUTP<="111100101"; WHEN "1111110000"=>OUTP<="111100111"; WHEN "1111110001"=>OUTP<="111101001"; WHEN "1111110010"=>OUTP<="111101010"; WHEN "1111110011"=>OUTP<="111101100"; WHEN "1111110101"=>OUTP<="111101111"; WHEN "1111110110"=>OUTP<="111110000"; WHEN "1111110111"=>OUTP<="111110010"; WHEN "1111111000"=>OUTP<="111110011"; WHEN "1111111001"=>OUTP<="111110101"; WHEN "1111111010"=>OUTP<="111110111"; WHEN "1111111011"=>OUTP<="111111010"; WHEN "1111111100"=>OUTP<="111111011"; WHEN "1111111101"=>OUTP<="111111101"; WHEN "1111111110"=>OUTP<="111111110"; WHEN "1111111111"=>OUTP<="000000000"; WHEN OTHERS=>OUTP<="000000000"; END CASE; END IF; END PROCESS; END ARCHITECTURE ART; 2.4.4 系统的整体组装DDS的VHDL源程序 --DDS.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DDS IS PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0); EN:IN STD_LOGIC; RESET:IN STD_LOGIC; CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END ENTITY DDS; ARCHITECTURE ART OF DDS IS COMPONENT SUM99 IS PORT(K:IN STD_LOGIC_VECTOR(9 DOWNTO 0); EN:IN STD_LOGIC; RESET:IN STD_LOGIC; CLK:IN STD_LOGIC; OUT1:OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END COMPONENT SUM99; COMPONENT REG1 IS PORT(D:IN STD_LOGIC_VECTOR(9 DOWNTO 0); CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END COMPONENT REG1; COMPONENT ROM IS PORT(CLK:IN STD_LOGIC; ADDR:IN STD_LOGIC_VECTOR(9 DOWNTO 0); OUTP:OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END COMPONENT ROM; COMPONENT REG2 IS PORT(D:IN STD_LOGIC_VECTOR(8 DOWNTO 0); CLK:IN STD_LOGIC; Q:OUT STD_LOGIC_VECTOR(8 DOWNTO 0)); END COMPONENT REG2; SIGNAL S1:STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL S2:STD_LOGIC_VECTOR(9 DOWNTO 0); SIGNAL S3:STD_LOGIC_VECTOR(8 DOWNTO 0); BEGIN U0:SUM99 PORT MAP(K=>K, EN=>EN, RESET=>RESET, CLK=>CLK, OUT1=>S1); U1:REG1 PORT MAP(D=>S1, CLK=>CLK, Q=>S2); U2:ROM PORT MAP(ADDR=>S2, CLK=>CLK, OUTP=>S3); U3:REG2 PORT MAP(D=>S3, CLK=>CLK, Q=>Q); END ARCHITECTURE ART; 信号发生器的VHDL源程序如下: --REG0.VHD LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY REG0 IS PORT(CLK: IN STD_LOGIC; LOCK:IN STD_LOGIC; Q: OUT STD_LOGIC_VECTOR(9 DOWNTO 0)); END ENTITY REG0; ARCHITECTURE ART OF REG0 IS BEGIN PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN IF LOCK='1' THEN Q<="0000011111"; --此时设定的频率控制字为1FH，可根据需要进行修改 END IF; END IF; END PROCESS; END ARCHITECTURE ART;