附录2：软件程序
投币模块主要程序如下：
library ieee；
use ieee.std_logic_1164.all；
entity toubi is
port (a1,a2,a5,en1,clk,reset:in std_logic；
bi：out integer range 0 to 15；
en： out std_logic);
end toubi；
architecture a of toubi is
signal state:integer range 0 to 1；
begin
process
variable qian：integer range 0 to 15；
begin
wait until clk=‘1’and clk' event；
if reset=‘1’ then state<=0；bi<=0；qian:=0；en<=‘0’；
else
case state is
when 0=>
if en1=‘1’ then if a1 =‘1’ then state<=1；bi<=1；qian：=1；en<=‘1’；
elsif a2=‘1’ then state<=1；bi<=2; qian：=2；en<=‘1’；
elsif a5=‘1’ then state<=1；qian:=5；bi<=5；en<=‘1’；
end if；
end if；
when 1=>
if en1=‘1’ then if a1=‘1’ then qian：=qian+1；bi<=qian；en<=‘1’；
elsif a2=‘1’ then qian：=qian+2；bi<=qian；en<=‘1’；
elsif a5=‘1’ then qian:=qian+5；bi<=qian；en<=‘1’；
end if；
商选择模块主要程序如下：
library ieee；
USE ieee.std_logic_1164.ALL；
ENTITY yima IS
PORT
( a1,a3,a4,a8,en2,reset : IN STD_LOGIC;
xuan_rg,xuan_yl,xuan_hb,xuan_schb:OUT STD_LOGIC；
d: OUT integer range 0 to 8 )；
END yima；
ARCHITECTURE a OF yima IS
BEGIN
process(a1,a3,a4,a8)
begin
if reset=‘0' then
if a1=‘1' and en2=‘1' then
d<=1；xuan_rg<=‘1'； xuan_yl<=‘0'；xuan_hb<=‘0'；xuan_schb<=‘0'；
elsif a3=‘1'then
d<=3；xuan_yl<=‘1'；xuan_rg<=‘0'；xuan_hb<=‘0'；xuan_schb<=‘0'；
elsif a4=‘1' and en2=‘1' then
d<=4； xuan_hb<=‘1'；xuan_yl<=‘0'；xuan_schb<=‘0'；
elsif a8=‘1' and en2=‘1' then
d<=8；xuan_schb<=‘1'；xuan_yl<=‘0'；xuan_rg<=‘0'；xuan_hb<=‘0'；
else d<=0;xuan_schb<='0';xuan_yl<='0';xuan_rg<='0’；xuan_hb<=‘0'；
end if;
else d<=0;xuan_schb<='0';xuan_yl<='0';xuan_rg<='0';xuan_hb<='0';
end if;
end process；
END a；
分频模块主要程序如下：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY fenpi IS
PORT(CLK:IN STD_LOGIC;
NEWCLK:OUT STD_LOGIC);
END fenpi;
ARCHITECTURE a OF fenpi IS
SIGNAL Q:INTEGER RANGE 0 TO 14;
SIGNAL DIVCLK: STD_LOGIC;
BEGIN
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF Q < 14 THEN Q <=Q+1;
ELSE DIVCLK <= NOT DIVCLK;Q <=0;
END IF;
END PROCESS;
NEWCLK <= DIVCLK;
END a;
计数模块主要程序如下：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity jishu is
port(clk,en,clr: in std_logic;
t: out std_logic);
end jishu;
architecture a of jishu is
signal bcd1n: std_logic_vector(3 downto 0);
begin
if (clr='1') then
bcd1n<="0000";
elsif(clk'event and clk='1') then
if (en='1') then
if (bcd1n="1001") then
bcd1n<="0000";
else
bcd1n<=bcd1n+'1';
end if;
end process;
process (clk,en,clr)
begin
if(clr='1') then
cd10n<="000";
elsif (clk'event and clk='1') then
if (en='1' and bcd1n="1001") then
if (bcd10n="011") then
bcd10n<="000";
else
if (en='1' and bcd10n="011") then
t<='1';
else
t<='0';
end if;
end process;
end a;
此段程序为十位计数的情况，当bcd为011（30）时发生进位，然后bcd10n归零。
出货模块主要程序如下：
library ieee;
use ieee.std_logic_1164.all;
ENTITY chuhuo IS
PORT
(xuan_rg,xuan_hb,xuan_yl,xuan_schb,en3 : IN STD_LOGIC;
chu_rg,chu_hb,chu_yl,chu_schb:OUT STD_LOGIC);
END chuhuo;
ARCHITECTURE a OF chuhuo IS
BEGIN
process
begin
if en3='0' then
chu_rg<='0'; chu_hb<='0';chu_schb<='0';chu_yl<='0';
else
if xuan_rg='1'then
chu_rg<='1'; chu_hb<='0';chu_schb<='0';chu_yl<='0';
elsif xuan_hb='1' then
chu_rg<='0'; chu_hb<='1';chu_schb<='0';chu_yl<='0';
elsif xuan_schb='1' then
chu_rg<='0'; chu_hb<='0';chu_schb<='1';chu_yl<='0';
elsif xuan_yl='1' then
end if;
end process;
END a;
显示模块程序如下：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY zhaoling IS
PORT(
Di : IN integer range 0 to 9;
a: OUT STD_LOGIC;
b : OUT STD_LOGIC;
c : OUT STD_LOGIC;
d : OUT STD_LOGIC;
e : OUT STD_LOGIC;
f : OUT STD_LOGIC;
g : OUT STD_LOGIC
);
END zhaoling;
ARCHITECTURE a OF zhaoling IS
BEGIN
Process (di)
type data_out is array (0 to 6) of std_logic;
variable outp:data_out;
begin
CASE di IS
WHEN 0 => outp:="1111110";
WHEN 1 => outp:="0110000";
WHEN 2 => outp:="1101101";
WHEN 3 => outp:="1111001";
WHEN 4 => outp:="0110011";
WHEN 5 => outp:="1011011";
WHEN 6 => outp:="1111110";
WHEN 7 => outp:="1011111";
WHEN 8 => outp:="1111111";
WHEN 9 => outp:="1111011";
WHEN OTHERS => null;
END CASE;
a <= outp(0);
b <= outp(1);
c <= outp(2);
d <= outp(3);
e <= outp(4);
f <= outp(5);
g <= outp(6);
end process;
END a;
主控模块主要程序如下：
library ieee;
use ieee.std_logic_1164.all;
package state_pack is
type state is(qa,qb);
end state_pack;
library ieee;
use ieee.std_logic_1164.all;
use work.state_pack.all;
entity zhukong is
port(start,clk,t:in std_logic;
d,b:in integer range 0 to 13;
en1,en2, reset, clr,en3:out std_logic;
c:out integer range 0 to 13;
di:out integer range 0 to 9);
end zhukong;
architecture a of zhukong is
signal current_state:state:=qa;
begin
process
variable var:integer range 0 to 13;
begin
wait until clk='1' and clk'event;
if start='1' then
current_state<=qa;
c<=b; en1<='0'; reset<='1';en2<='0';clr<='1';en3<='0';di<=0;
else
case current_state is
when qa=> if d=0 then
current_state<=qa; en1<='0';en2<='1';clr<='0';c<=0;reset<='0';di<=0;
else current_state<=qb; var:=d; en2<='0';
