实验 1--一位全加器的设计======
--程序 1:或门逻辑描述
LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY or2a IS
PORT (a, b :IN STD_LOGIC;
c : OUT STD_LOGIC );
END ENTITY or2a;
ARCHITECTURE one OF or2a IS
BEGIN
c <= a OR b ;
END ARCHITECTURE one;
--程序 2:半加器描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY h_adder IS
PORT (a, b : IN STD_LOGIC;
co, so : OUT STD_LOGIC);
END ENTITY h_adder;
ARCHITECTURE fh1 OF h_adder is
BEGIN
so <= NOT(a XOR (NOT b)) ;
co <= a AND b ;
END ARCHITECTURE fh1;
--程序 3:1 位二进制全加器顶层设计描述
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY f_adder IS
PORT (ain,bin,cin : IN STD_LOGIC;
cout,sum : OUT STD_LOGIC );
END ENTITY f_adder;
ARCHITECTURE fd1 OF f_adder IS
COMPONENT h_adder
PORT ( a,b : IN STD_LOGIC;
co,so : OUT STD_LOGIC);
END COMPONENT ;
COMPONENT or2a
PORT (a,b : IN STD_LOGIC;
c : OUT STD_LOGIC);
END COMPONENT;
SIGNAL d,e,f : STD_LOGIC;
BEGIN