PC1600 and PC2100 DDR SDRAM Unbuffered DIMM
Design Specification
Revision 1.1
June 29, 2001
Page 2 Revision 1.1
Table of Contents PC1600/PC2100 DDR SDRAM Unbuffered DIMM Design Specification
Table of Contents
Table of Contents .........................................................................................................................................................2
Product Description .....................................................................................................................................................3
Product Family Attributes....................................................................................................................................... 3
Environmental Requirements .....................................................................................................................................5
Architecture ..................................................................................................................................................................5
Absolute Maximum Ratings ................................................................................................................................... 5
Pin Description........................................................................................................................................................ 5
Input/Output Functional Description ...................................................................................................................... 6
184-Pin DDR SDRAM DIMM Pin Assignments................................................................................................... 7
Block Diagram: Raw Card Version A, x72 ............................................................................................................ 8
Block Diagram: Raw Card Version A, x64 ............................................................................................................ 9
Block Diagram: Raw Card Version B, x64........................................................................................................... 10
Block Diagram: Raw Card Version B, x72........................................................................................................... 11
Block Diagram: Raw Card Version C, x64........................................................................................................... 12
Block Diagram: Raw Card Version C, x72........................................................................................................... 13
Logical Clock Net Structures................................................................................................................................ 14
Component Details .....................................................................................................................................................15
Pin Assignments for 64Mb, 128Mb, 256Mb and 512Mb DDR SDRAM Planar Components............................ 15
DDR SDRAM Component Specifications............................................................................................................ 16
Unbuffered DIMM Details ........................................................................................................................................16
SDRAM Module Configurations (Reference Designs) ........................................................................................ 16
DDR Unbuffered Design File Releases ................................................................................................................ 17
Input Loading Matrix............................................................................................................................................ 17
Component Types and Placement......................................................................................................................... 18
Example Raw Card A Component Placement...................................................................................................... 18
Example Raw Card B Component Placement ...................................................................................................... 19
Example Raw Card C Component Placement ...................................................................................................... 19
DIMM Wiring Details ................................................................................................................................................20
Signal Groups........................................................................................................................................................ 20
General Net Structure Routing Guidelines ........................................................................................................... 20
Explanation of Net Structure Diagrams................................................................................................................ 21
Net Structure Example.......................................................................................................................................... 21
Clock Net Structures............................................................................................................................................. 22
Signal Net Structures ............................................................................................................................................ 23
Cross Section Recommendations.......................................................................................................................... 34
Decoupling............................................................................................................................................................ 34
PC1600/PC2100 DDR SDRAM Unbuffered DIMM Design Specification Table of Contents
Revision 1.1 Page 3
Design Target ..............................................................................................................................................................35
Address setup/hold flight times ............................................................................................................................ 35
Clock Skew Contributions (tSKEW).................................................................................................................... 35
Serial PD Definition ...................................................................................................................................................36
Serial Presence Detect Example Raw Card Version ’B’...................................................................................... 36
Serial Presence Detect Component Specification................................................................................................. 37
Product Label .............................................................................................................................................................38
DIMM Mechanical Specifications ............................................................................................................................39
Simplified Mechanical Drawing with Keying Positions ...................................................................................... 39
Clocking Timing Methodology .................................................................................................................................40
Unbuffered DIMM Differential Clock Reference Net.......................................................................................... 40
Revision Log ...............................................................................................................................................................41
Page 4 Revision 1.1
1. Product Description PC1600/PC2100 DDR SDRAM Unbuffered DIMM Design Specification
1. Product Description
This specification defines the electrical and mechanical requirements for 184-pin, 2.5 Volt (V
DD
)/ 2.5 Volt (V
DDQ
),
Unbuffered, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR SDRAM DIMMs).These
DDR DIMMs are intended for use as main memory when installed in PCs. The DDR DIMMs must permit operation
with a new address every clock cycle in PC1600 and PC2100 environments.
Reference design examples are included which provide an initial basis for Unbuffered DDR DIMM designs. Modifica-
tions to these reference designs may be required to meet all system timing, signal integrity and thermal requirements for
PC1600 and PC2100 support. All Unbuffered DIMM implementations must use simulations and lab verification to
ensure proper timing requirements and signal integrity in the design.
This specification largely follows the JEDEC defined 184-pin Unbuffered DDR SDRAM DIMM product. (Refer to
JEDEC standard JESD21-C, Section 4.5.10, at www.jedec.org).
Product Family Attributes
DIMM Organization x64, x72 ECC Notes
DIMM Dimensions (max) 5.256" x 1.256" x 0.157"
Pin Count 184
DDR SDRAMs Supported 64Mb, 128Mb, 256Mb, 512Mb
Capacity 32MB - 1GB
Serial PD Consistent with JEDEC JC 42.5 Item 849A
Voltage Options
2.5 Volt V
DD
/V
DDQ
2.3 Volt to 3.6 Volt V
DD
SPD
All DDR modules use a common V
DD
-
V
DDQ
power plane. They are tied together
on the DIMM, but by standard definition
are supported on the pinout to accommodate
future enhancements.
Interface SSTL_2
Note 1: V
DD
SPD is not tied to V
DD
or V
DDQ
on the DDR DIMM.
PC1600/PC2100 DDR SDRAM Unbuffered DIMM Design Specification 2. Environmental Requirements
Revision 1.1 Page 5
2. Environmental Requirements
184-pin Unbuffered DDR SDRAM DIMMs are intended for use in standard office environments that have limited
capacity for heating and air conditioning.
3. Architecture
*The V
DD
and V
DDQ
pins are tied to the single power-plane on these designs. See page 35.
Absolute Maximum Ratings
Symbol Parameter Rating Units Notes
T
OPR
Operating Temperature (ambient) 0 to +55
°C1
H
OPR
Operating Humidity (relative) 10 to 90
%1
T
STG
Storage Temperature -50 to +100
°C
1
H
STG
Storage Humidity (without condensation) 5 to 95 % 1
Barometric Pressure (operating & storage) 105 to 69 K Pascal 1, 2
1. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or
above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Up to 9850 ft.
Pin Description
Pin Name Description Pin Name Description
A0 - A13 SDRAM address bus CK0 - CK2
SDRAM clock (positive lines of 3 differ-
ential pairs)
BA0 - BA1 SDRAM bank select CK0
- CK2
SDRAM clock (negative lines of these
three pairs)
DQ0 - DQ63 DIMM memory data bus SCL IIC serial bus clock for EEPROM
CB0 - CB7 DIMM ECC check bits SDA IIC serial bus data line for EEPROM
/RAS SDRAM row address strobe SA0 - SA2 IIC slave address select for EEPROM
/CAS SDRAM column address strobe
V
DD
*
SDRAM positive power supply
/WE SDRAM write strobe
V
DDQ
*
SDRAM I/O Driver positive power sup-
ply
/S0 - /S1
SDRAM chip select lines (Phys. banks 0
and 1)
VREF SDRAM I/O reference supply
CKE0 - CKE1 SDRAM clock enable lines
V
SS
Power supply return (ground)
DQS0 - DQS8 SDRAM low data strobes
V
DD
SPD
Serial EEPROM positive power supply
(2.3 Volts to 3.6 Volts)--V
DD
SPD is not
connected to V
DD
or V
DDQ
DM(0-8)/DQS(9-17)
SDRAM low data masks/high data strobes
(x4, 2 Phys. banks)
NC Spare pins (no connect)
V
DD
ID V
DD
identification flag
