DAC_TLC5620.zip_DA芯片；verilog_cbx_args.txt_dacverilog

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DAC_TLC5620.zip （42个子文件）

DAC_TLC5620

img

文件夹模版.txt 216B

rtl

TCL5620_TOP.v.bak 124B

TCL5620_TOP.v 604B

TLC5620_CTRL.v 3KB

TLC5620_CTRL.v.bak 599B

testbench

TLC5620_CTRL_tb.v.bak 220B

TLC5620_CTRL_tb.v 1KB

doc

TLC5620.pdf 217KB

~$_多通道串行DAC驱动设计与验证.docx 162B

TLC5620_CTRL.vsdx 21KB

DAC电路.JPG 67KB

17_多通道串行DAC驱动设计与验证.docx 967KB

参考源.JPG 47KB

prj

greybox_tmp

cbx_args.txt 221B

TLC5620_CTRL.qpf 1KB

TLC5620_CTRL.ipinfo 275B

TLC5620_CTRL.sld_design_entry.sci 202B

TLC5620_CTRL.db_info 140B

TLC5620_CTRL.qsf 4KB

TLC5620_CTRL_nativelink_simulation.rpt 858B

greybox_tmp

cbx_args.txt 221B

CtrlWordSource.v 4KB

CtrlWordSource_bb.v 3KB

CtrlWordSource.qip 313B

TLC5620_TOP.map 189B

CtrlWordSource.qip 0B

TLC5620_TOP.jic 2MB

output_files

TLC5620_CTRL.sta.summary 2KB

TLC5620_CTRL.done 26B

TLC5620_CTRL.jdi 5KB

TLC5620_CTRL.eda.rpt 8KB

TLC5620_CTRL.flow.rpt 10KB

TLC5620_CTRL.sta.rpt 630KB

TLC5620_CTRL.fit.smsg 703B

TLC5620_CTRL.pin 32KB

TLC5620_CTRL.map.summary 480B

TLC5620_CTRL.fit.summary 620B

TLC5620_CTRL.map.rpt 45KB

TLC5620_CTRL.asm.rpt 8KB

TLC5620_CTRL.fit.rpt 250KB

TLC5620_CTRL.sof 351KB

TLC5620_CTRL.qws 2KB

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Four 8-Bit Voltage Output DACs

5-V Single-Supply Operation

Serial Interface

High-Impedance Reference Inputs

Programmable 1 or 2 Times Output Range

Simultaneous Update Facility

Internal Power-On Reset

Low-Power Consumption

Half-Buffered Output

applications

Programmable Voltage Sources

Digitally Controlled Amplifiers/Attenuators

Mobile Communications

Automatic Test Equipment

Process Monitoring and Control

Signal Synthesis

description

The TLC5620C and TLC5620I are quadruple 8-bit voltage output digital-to-analog converters (DACs) with

buffered reference inputs (high impedance). The DACs produce an output voltage that ranges between either

one or two times the reference voltages and GND, and the DACs are monotonic. The device is simple to use,

running from a single supply of 5 V. A power-on reset function is incorporated to ensure repeatable start-up

conditions.

Digital control of the TLC5620C and TLC5620I are over a simple three-wire serial bus that is CMOS compatible

and easily interfaced to all popular microprocessor and microcontroller devices. The 11-bit command word

comprises eight bits of data, two DAC-select bits, and a range bit, the latter allowing selection between the times

1 or times 2 output range. The DAC registers are double buffered, allowing a complete set of new values to be

written to the device, then all DAC outputs are updated simultaneously through control of LDAC. The digital

inputs feature Schmitt triggers for high noise immunity.

The 14-terminal small-outline (D) package allows digital control of analog functions in space-critical

applications. The TLC5620C is characterized for operation from 0°C to 70°C. The TLC5620I is characterized

for operation from –40°C to 85°C. The TLC5620C and TLC5620I do not require external trimming.

AVAILABLE OPTIONS

PACKAGE

SMALL OUTLINE

(D)

PLASTIC DIP

(N)

0°C to 70°C TLC5620CD TLC5620CN

–40°C to 85°C TLC5620ID TLC5620IN

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

REFA

REFB

REFC

REFD

DATA

CLK

LDAC

DACA

DACB

DACC

DACD

LOAD

N OR D PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

DAC

Power-On

Reset

Serial

Interface

× 2

LatchLatch

Latch

DAC

× 2

LatchLatch

Latch Latch

DAC

× 2

LDAC

REFA

–

REFB

REFC

CLK

REFD

DATA

LOAD

DACA

DACB

DACC

DACD

Terminal Functions

TERMINAL

I/O

DESCRIPTION

NAME NO.

I/O

DESCRIPTION

CLK 7 I Serial interface clock. The input digital data is shifted into the serial interface

DACA 12 O DAC A analog output

DACB 11 O DAC B analog output

DACC 10 O DAC C analog output

DACD 9 O DAC D analog output

DATA 6 I Serial interface digital data input. The digital code for the DAC is clocked into the

serial interface register serially. Each data bit is clocked into the register on the

falling edge of the clock signal.

GND 1 I Ground return and reference terminal

LDAC 13 I Load DAC. When the LDAC signal is high, no DAC output updates occur when

the input digital data is read into the serial interface. The DAC outputs are only

updated when LDAC is taken from high to low.

LOAD 8 I Serial Interface load control. When LDAC is low, the falling edge of the LOAD

signal latches the digital data into the output latch and immediately produces the

analog voltage at the DAC output terminal.

REFA 2 I Reference voltage input to DAC A. This voltage defines the output analog range.

REFB 3 I Reference voltage input to DAC B. This voltage defines the output analog range.

REFC 4 I Reference voltage input to DAC C. This voltage defines the output analog range.

REFD 5 I Reference voltage input to DAC D. This voltage defines the output analog range.

14 I Positive supply voltage

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

detailed description

The TLC5620 is implemented using four resistor-string DACs. The core of each DAC is a single resistor with

256 taps, corresponding to the 256 possible codes listed in Table 1. One end of each resistor string is connected

to the GND terminal and the other end is fed from the output of the reference input buffer. Monotonicity is

maintained by use of the resistor strings. Linearity depends upon the matching of the resistor elements and upon

the performance of the output buffer. Since the inputs are buffered, the DACs always present a high-impedance

load to the reference source.

Each DAC output is buffered by a configurable-gain output amplifier that can be programmed to times 1 or times

2 gain.

On power up, the DACs are reset to CODE 0.

Each output voltage is given by:

(DACA|B|C|D)

REF

CODE

256

)

RNG bit value)

where CODE is in the range 0 to 255 and the range (RNG) bit is 0 or 1 within the serial control word.

Table 1. Ideal Output Transfer

D7 D6 D5 D4 D3 D2 D1 D0 OUTPUT VOLTAGE

0 0 0 0 0 0 0 0 GND

0 0000001 (1/256) × REF (1+RNG)

• ••••••• •

0 1111111 (127/256) × REF (1+RNG)

1 0000000 (128/256) × REF (1+RNG)

• ••••••• •

1 1 1 1 1 1 1 1 (255/256) × REF (1+RNG)

data interface

With LOAD high, data is clocked into the DATA terminal on each falling edge of CLK. Once all data bits have

been clocked in, LOAD is pulsed low to transfer the data from the serial input register to the selected DAC as

shown in Figure 1. When LDAC is low, the selected DAC output voltage is updated when LOAD goes low. When

LDAC is high during serial programming, the new value is stored within the device and can be transferred to

the DAC output at a later time by pulsing LDAC low as shown in Figure 2. Data is entered most significant bit

(MSB) first. Data transfers using two 8-clock cycle periods are shown in Figures 3 and 4.

RNGA1 A0 D7 D6 D5 D4 D3 D2 D1 D0

DAC Update

CLK

DATA

LOAD

su(DATA-CLK)

v(DATA-CLK)

su(CLK-LOAD)

w(LOAD)

su(LOAD-CLK)

Figure 1. LOAD-Controlled Update (LDAC = Low)

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RNG

CLK

DATA

LOAD

LDAC

DAC Update

A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

su(DATA-CLK)

v(DATA-CLK)

w(LDAC)

su(LOAD-LDAC)

Figure 2. LDAC-Controlled Update

ÎÎÎÎÎÎ

ÎÎÎ

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

CLK

DATA

LOAD

LDAC

CLK Low

Figure 3. Load-Controlled Update Using 8-Bit Serial Word (LDAC = Low)

ÎÎÎÎÎÎÎ

ÎÎÎÎ

A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0

CLK

DATA

LOAD

LDAC

CLK Low

Figure 4. LDAC-Controlled Update Using 8-Bit Serial Word

Table 2 lists the A1 and A0 bits and the selection of the updated DACs. The RNG bit controls the DAC output

range. When RNG = low, the output range is between the applied reference voltage and GND, and when

RNG = high, the range is between twice the applied reference voltage and GND.

Table 2. Serial Input Decode

A1 A0 DAC UPDATED

0 0 DACA

0 1 DACB

1 0 DACC

1 1 DACD

TLC5620C, TLC5620I

QUADRUPLE 8-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS081E – NOVEMBER 1994 – REVISED NOVEMBER 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

linearity, offset, and gain error using single-end supplies

When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With

a positive offset voltage, the output voltage changes on the first code change. With a negative offset the output

voltage may not change with the first code depending on the magnitude of the offset voltage.

The output amplifier attempts to drive the output to a negative voltage. However, because the most negative

supply rail is ground, the output cannot drive below ground and clamps the output at 0 V.

The output voltage then remains at zero until the input code value produces a sufficient positive output voltage

to overcome the negative offset voltage, resulting in the transfer function shown in Figure 5.

DAC Code

Output

Voltage

0 V

Negative

Offset

Figure 5. Effect of Negative Offset (Single Supply)

This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the

dotted line if the output buffer could drive below ground.

For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after

offset and full scale are adjusted out or accounted for in some way. However, single-supply operation does not

allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity

is measured between full-scale code and the lowest code that produces a positive output voltage. The code is

calculated from the maximum specification for the negative offset voltage.

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