radeon_legacy_tv.rar_out

#include <drm/drmP.h> #include <drm/drm_crtc_helper.h> #include "radeon.h" /* * Integrated TV out support */ /* * Limits of h/v positions (hPos & vPos) */ #define MAX_H_POSITION 5 /* Range: [-5..5], negative is on the left, 0 is default, positive is on the right */ #define MAX_V_POSITION 5 /* Range: [-5..5], negative is up, 0 is default, positive is down */ /* * Unit for hPos (in TV clock periods) */ #define H_POS_UNIT 10 /* * Indexes in h. code timing table for horizontal line position adjustment */ #define H_TABLE_POS1 6 #define H_TABLE_POS2 8 /* * Limits of hor. size (hSize) */ #define MAX_H_SIZE 5 /* Range: [-5..5], negative is smaller, positive is larger */ /* tv standard constants */ #define NTSC_TV_CLOCK_T 233 #define NTSC_TV_VFTOTAL 1 #define NTSC_TV_LINES_PER_FRAME 525 #define NTSC_TV_ZERO_H_SIZE 479166 #define NTSC_TV_H_SIZE_UNIT 9478 #define PAL_TV_CLOCK_T 188 #define PAL_TV_VFTOTAL 3 #define PAL_TV_LINES_PER_FRAME 625 #define PAL_TV_ZERO_H_SIZE 473200 #define PAL_TV_H_SIZE_UNIT 9360 /* tv pll setting for 27 mhz ref clk */ #define NTSC_TV_PLL_M_27 22 #define NTSC_TV_PLL_N_27 175 #define NTSC_TV_PLL_P_27 5 #define PAL_TV_PLL_M_27 113 #define PAL_TV_PLL_N_27 668 #define PAL_TV_PLL_P_27 3 /* tv pll setting for 14 mhz ref clk */ #define NTSC_TV_PLL_M_14 33 #define NTSC_TV_PLL_N_14 693 #define NTSC_TV_PLL_P_14 7 #define PAL_TV_PLL_M_14 19 #define PAL_TV_PLL_N_14 353 #define PAL_TV_PLL_P_14 5 #define VERT_LEAD_IN_LINES 2 #define FRAC_BITS 0xe #define FRAC_MASK 0x3fff struct radeon_tv_mode_constants { uint16_t hor_resolution; uint16_t ver_resolution; enum radeon_tv_std standard; uint16_t hor_total; uint16_t ver_total; uint16_t hor_start; uint16_t hor_syncstart; uint16_t ver_syncstart; unsigned def_restart; uint16_t crtcPLL_N; uint8_t crtcPLL_M; uint8_t crtcPLL_post_div; unsigned pix_to_tv; }; static const uint16_t hor_timing_NTSC[MAX_H_CODE_TIMING_LEN] = { 0x0007, 0x003f, 0x0263, 0x0a24, 0x2a6b, 0x0a36, 0x126d, /* H_TABLE_POS1 */ 0x1bfe, 0x1a8f, /* H_TABLE_POS2 */ 0x1ec7, 0x3863, 0x1bfe, 0x1bfe, 0x1a2a, 0x1e95, 0x0e31, 0x201b, 0 }; static const uint16_t vert_timing_NTSC[MAX_V_CODE_TIMING_LEN] = { 0x2001, 0x200d, 0x1006, 0x0c06, 0x1006, 0x1818, 0x21e3, 0x1006, 0x0c06, 0x1006, 0x1817, 0x21d4, 0x0002, 0 }; static const uint16_t hor_timing_PAL[MAX_H_CODE_TIMING_LEN] = { 0x0007, 0x0058, 0x027c, 0x0a31, 0x2a77, 0x0a95, 0x124f, /* H_TABLE_POS1 */ 0x1bfe, 0x1b22, /* H_TABLE_POS2 */ 0x1ef9, 0x387c, 0x1bfe, 0x1bfe, 0x1b31, 0x1eb5, 0x0e43, 0x201b, 0 }; static const uint16_t vert_timing_PAL[MAX_V_CODE_TIMING_LEN] = { 0x2001, 0x200c, 0x1005, 0x0c05, 0x1005, 0x1401, 0x1821, 0x2240, 0x1005, 0x0c05, 0x1005, 0x1401, 0x1822, 0x2230, 0x0002, 0 }; /********************************************************************** * * availableModes * * Table of all allowed modes for tv output * **********************************************************************/ static const struct radeon_tv_mode_constants available_tv_modes[] = { { /* NTSC timing for 27 Mhz ref clk */ 800, /* horResolution */ 600, /* verResolution */ TV_STD_NTSC, /* standard */ 990, /* horTotal */ 740, /* verTotal */ 813, /* horStart */ 824, /* horSyncStart */ 632, /* verSyncStart */ 625592, /* defRestart */ 592, /* crtcPLL_N */ 91, /* crtcPLL_M */ 4, /* crtcPLL_postDiv */ 1022, /* pixToTV */ }, { /* PAL timing for 27 Mhz ref clk */ 800, /* horResolution */ 600, /* verResolution */ TV_STD_PAL, /* standard */ 1144, /* horTotal */ 706, /* verTotal */ 812, /* horStart */ 824, /* horSyncStart */ 669, /* verSyncStart */ 696700, /* defRestart */ 1382, /* crtcPLL_N */ 231, /* crtcPLL_M */ 4, /* crtcPLL_postDiv */ 759, /* pixToTV */ }, { /* NTSC timing for 14 Mhz ref clk */ 800, /* horResolution */ 600, /* verResolution */ TV_STD_NTSC, /* standard */ 1018, /* horTotal */ 727, /* verTotal */ 813, /* horStart */ 840, /* horSyncStart */ 633, /* verSyncStart */ 630627, /* defRestart */ 347, /* crtcPLL_N */ 14, /* crtcPLL_M */ 8, /* crtcPLL_postDiv */ 1022, /* pixToTV */ }, { /* PAL timing for 14 Mhz ref clk */ 800, /* horResolution */ 600, /* verResolution */ TV_STD_PAL, /* standard */ 1131, /* horTotal */ 742, /* verTotal */ 813, /* horStart */ 840, /* horSyncStart */ 633, /* verSyncStart */ 708369, /* defRestart */ 211, /* crtcPLL_N */ 9, /* crtcPLL_M */ 8, /* crtcPLL_postDiv */ 759, /* pixToTV */ }, }; #define N_AVAILABLE_MODES ARRAY_SIZE(available_tv_modes) static const struct radeon_tv_mode_constants *radeon_legacy_tv_get_std_mode(struct radeon_encoder *radeon_encoder, uint16_t *pll_ref_freq) { struct drm_device *dev = radeon_encoder->base.dev; struct radeon_device *rdev = dev->dev_private; struct radeon_crtc *radeon_crtc; struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; const struct radeon_tv_mode_constants *const_ptr; struct radeon_pll *pll; radeon_crtc = to_radeon_crtc(radeon_encoder->base.crtc); if (radeon_crtc->crtc_id == 1) pll = &rdev->clock.p2pll; else pll = &rdev->clock.p1pll; if (pll_ref_freq) *pll_ref_freq = pll->reference_freq; if (tv_dac->tv_std == TV_STD_NTSC || tv_dac->tv_std == TV_STD_NTSC_J || tv_dac->tv_std == TV_STD_PAL_M) { if (pll->reference_freq == 2700) const_ptr = &available_tv_modes[0]; else const_ptr = &available_tv_modes[2]; } else { if (pll->reference_freq == 2700) const_ptr = &available_tv_modes[1]; else const_ptr = &available_tv_modes[3]; } return const_ptr; } static long YCOEF_value[5] = { 2, 2, 0, 4, 0 }; static long YCOEF_EN_value[5] = { 1, 1, 0, 1, 0 }; static long SLOPE_value[5] = { 1, 2, 2, 4, 8 }; static long SLOPE_limit[5] = { 6, 5, 4, 3, 2 }; static void radeon_wait_pll_lock(struct drm_encoder *encoder, unsigned n_tests, unsigned n_wait_loops, unsigned cnt_threshold) { struct drm_device *dev = encoder->dev; struct radeon_device *rdev = dev->dev_private; uint32_t save_pll_test; unsigned int i, j; WREG32(RADEON_TEST_DEBUG_MUX, (RREG32(RADEON_TEST_DEBUG_MUX) & 0xffff60ff) | 0x100); save_pll_test = RREG32_PLL(RADEON_PLL_TEST_CNTL); WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test & ~RADEON_PLL_MASK_READ_B); WREG8(RADEON_CLOCK_CNTL_INDEX, RADEON_PLL_TEST_CNTL); for (i = 0; i < n_tests; i++) { WREG8(RADEON_CLOCK_CNTL_DATA + 3, 0); for (j = 0; j < n_wait_loops; j++) if (RREG8(RADEON_CLOCK_CNTL_DATA + 3) >= cnt_threshold) break; } WREG32_PLL(RADEON_PLL_TEST_CNTL, save_pll_test); WREG32(RADEON_TEST_DEBUG_MUX, RREG32(RADEON_TEST_DEBUG_MUX) & 0xffffe0ff); } static void radeon_legacy_tv_write_fifo(struct radeon_encoder *radeon_encoder, uint16_t addr, uint32_t value) { struct drm_device *dev = radeon_encoder->base.dev; struct radeon_device *rdev = dev->dev_private; uint32_t tmp; int i = 0; WREG32(RADEON_TV_HOST_WRITE_DATA, value); WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr); WREG32(RADEON_TV_HOST_RD_WT_CNTL, addr | RADEON_HOST_FIFO_WT); do { tmp = RREG32(RADEON_TV_HOST_RD_WT_CNTL); if ((tmp & RADEON_HOST_FIFO_WT_ACK) == 0) break; i++; } while (i < 10000); WREG32(RADEON_TV_HOST_RD_WT_CNTL, 0); } #if 0 /