LIBRARY IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_unsigned.ALL;
entity sb is
port(clk,k1,k2:in std_logic;
date:out std_logic_vector( 6 downto 0 ));
end sb;
architecture behave of sb is
signal f: std_logic_vector(7 downto 0);
signal clk1,clk2,clk3,m: std_logic ;
type states is (s0,s1,s2,s3,s4,s5,s6,s7,s8);
signal st:states;
begin
process(clk)
begin
if clk'event and clk ='1'then
f<=f+1;
end if;
end process;
process(clk,f)
begin
if clk'event and clk ='1' then
clk1<=f(0);
clk2<=f(1);
clk3<=f(2);
end if;
end process;
process(k1,k2)
begin
if(k1='0' and k2='0')then m<=clk;
elsif(k1='0' and k2='1')then m<=clk1;
elsif(k1='1' and k2='0')then m<=clk2;
elsif(k1='1' and k2='1')then m<=clk3;
end if;
end process;
process(st)
begin
if m'event and m='1'then
case st is
when s0=>date<="1110110";st<=s1;
when s1=>date<="1011011";st<=s2;
when s2=>date<="1000111";st<=s3;
when s3=>date<="1111110";st<=s4;
when s4=>date<="0011111";st<=s5;
when s5=>date<="1111011";st<=s6;
when s6=>date<="1001111";st<=s7;
when s7=>date<="1111111";st<=s8;
when s8=>date<="1110000";st<=s0;
end case;
end if;
end process;
end behave;
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