high-perf-full-featured.zip_high

readme - High Performance Full Featured Design with Bridges Overview: This design is provided as a higher performance version of the full featured design available in the Nios II EDS. A pipeline bridge has been inserted between the Nios II and DMA Avalon-MM masters and all non-memory based components. Using the bridge the topology of the hardware is controlled thereby increasing the overall fmax of the design without adding additional memory latency. The key features of this design are as follows: - A DMA peripheral for high-speed data transfers - An example custom instruction connected to the Nios II CPU - A performance counter capable of clock cycle accuracy - A pair of tightly coupled memories with the same latency as cache memory - Floating point math and interrupt vector custom instructions - Performance of 107DMIPs when .text, .rodata, .rwdata linked to SSRAM; heap and stack in tightly coupled data memory Since this design is based on the full featured design from the Nios II EDS the software support is identical. The key differences between the design provided in the Nios II EDS and this one are as follows: - Floating point math hardware addition - Reduced JTAG debug module support from level 4 to level 1 - Fmax increase (100MHz) Contents of the System: - Nios II/f Core (w/ floating point math hardware) - JTAG Debug Module (Level 1) - Onchip Tightly Coupled Data Memory (8kB) - Onchip Tightly Coupled Instruction Memory (4kB) - DDR SDRAM Controller (32MB) - SSRAM Controller (2MB) - CFI Flash Memory Interface (16MB) - DMA Controller - EPCS Controller (with bootloader) - JTAG UART - UART (RS-232) - Two Timers - Ethernet Interface - LED PIO - Seven Segment Display PIO - Push Button PIO - LCD Display Interface - Performance Counter - System ID Peripheral Supported Software Examples: - Blank Project - Hello World - Board Diagnostic - Count Binary - Dhrystone - Hello Free-Standing - Hello LED - Hello MicroC/OS II - Hello World Small - Host File System - MicroC/OS-II Message Box - Memory Test - MicroC/OS-II Tutorial - Simple Sockets Server - Web Server - Zip File System - TCM (Tightly Coupled Memory) Resource Utilization (% total): - Total logic elements: 14658 (44%) - Total combinational functions: 11529 (35%) - Dedicated logic registers: 8773 (26%) - Total block memory bits: 169344 (35%) - Embedded multiplier 9-bit elements: 11 (16%) - Total PLLs: 1 (17%) Recommended usage: If you choose to use this design for your own product and wish to increase the fmax further it is recommended to reduce the Nios II and DMA interconnect. This design connects Nios II and the DMA to all memories in the system which may not be necessary for your product. Keep in mind that the SSRAM and DDR-SDRAM each have an Fmax of 167MHz.