uart.rar_arm uart_arm 串口_arm9_arm9 uart_uart arm9

//==================================================================== // File Name : 2410iis.c // Function : S3C2410 IIS (UDA1341) Record & Play Test Program // (DMA2, Double Buffer, Record, Play) // Program : Shin, On Pil (SOP) // Date : October 01, 2002 // Version : 0.0 // History // 0.0 : Programming start (March 06, 2002) -> SOP // 0.1 : Added Slave mode Test Program(July 24, 2002) -> KWT(Tark), SOP // Optimization (December 09, 2002) -> SOP //==================================================================== #include "2410addr.h" #include "2410lib.h" #include "def.h" #include "2410iis.h" void ChangeDMA2(void); void IIS_PortSetting(void); void _WrL3Addr(U8 data); void _WrL3Data(U8 data,int halt); static void AdjVolume(U8 dir); static void PlayPause(void); static void Muting(void); void __irq DMA2_Done(void); void __irq DMA2_Rec_Done(void); void __irq RxInt(void); #define L3C (1<<4) //GPB4 = L3CLOCK #define L3D (1<<3) //GPB3 = L3DATA #define L3M (1<<2) //GPB2 = L3MODE #define PLAY 0 #define RECORD 1 #define REC_LEN 0x80000 //512K Bytes //#define REC_LEN 0x100000 //1,048,576 Bytes #define DataCount 0x10000 //IIS Master/Slave Data Rx/Tx Count #define DataDisplay 0x100 //IIS Master Data Display Count //#define DataDisplay 0x10000 //IIS Master Data Display Count //#define DataCount 0x100 //IIS Master/Slave Data Rx/Tx Count #define PollMode 0 //1: Polling Mode #define DMA2Mode 1 //1: DMA2 Mode unsigned char *Buf,*_temp; unsigned short *rec_buf; volatile unsigned int size = 0; volatile unsigned int fs = 0; volatile char which_Buf = 1; volatile char Rec_Done = 0; volatile char mute = 1; //------------------------------------------------------------------------------ // SMDK2410 IIS Configuration // GPB4 = L3CLOCK, GPB3 = L3DATA, GPB2 = L3MODE // GPE4 = I2SSDO, GPE3 = I2SSDI, GPE2 = CDCLK, GPE1 = I2SSCLK, GPE0 = I2SLRCK //------------------------------------------------------------------------------ extern U32 downloadFileSize; extern U32 downloadAddress; //*********************[ Test_Iis ] ********************************* void Test_Iis(void) { unsigned int save_B, save_E, save_PB, save_PE; Uart_TxEmpty(1);//Uart_TxEmpty(0); ChangeClockDivider(1,1); //1:2:4 ChangeMPllValue(0x96,0x5,0x1); //FCLK=135.428571MHz (PCLK=33.857142MHz) Uart_Init(33857142,115200); Uart_Printf("[ IIS test (Play) using UDA1341 CODEC ]\n"); save_B = rGPBCON; save_E = rGPECON; save_PB = rGPBUP; save_PE = rGPEUP; IIS_PortSetting(); pISR_UART0 = (unsigned)RxInt; //串口接收数据中断 pISR_DMA2 = (unsigned)DMA2_Done; ClearPending(BIT_UART0); ClearPending(BIT_DMA2); EnableSubIrq(BIT_SUB_RXD0);//rINTSUBMSK = ~(BIT_SUB_RXD0); EnableIrq(BIT_DMA2);//rINTMSK = ~(BIT_EINT0 | BIT_UART0 | BIT_DMA2); //Non-cacheable area = 0x31000000 ~ 0x33feffff size = downloadFileSize; Buf = (U8 *)downloadAddress; printf("\nFile length = %d, Address = 0x%x\n", size-10, Buf); size = *(U32 *)(Buf+0x28); fs = *(U32 *)(Buf+0x18); printf("Sample Size = %d\n",size); printf("Sampling Frequency = %d Hz\n",fs); // printf("Press any key to play...\n"); // printf("If you want to mute or no mute push the 'EIN0' key repeatedly\n"); // getch(); Init1341(PLAY); //DMA2 Initialize rDISRC2 = (int)(Buf + 0x30); //0x31000030~(Remove header) rDISRCC2 = (0<<1) + (0<<0); //The source is in the system bus(AHB), Increment rDIDST2 = ((U32)IISFIFO); //IISFIFO rDIDSTC2 = (1<<1) + (1<<0); //The destination is in the peripheral bus(APB), Fixed rDCON2 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(0<<24)+(1<<23)+(0<<22)+(1<<20)+(size/4); //1010 0000 1001 xxxx xxxx xxxx xxxx xxxx //Handshake[31], Sync PCLK[30], CURR_TC Interrupt Request[29], Single Tx[28], Single service[27], //I2SSDO[26:24], DMA source selected[23],Auto-reload[22], Half-word[21:20], size/2[19:0] rDMASKTRIG2 = (0<<2) + (1<<1) + (0<<0); //No-stop[2], DMA2 channel On[1], No-sw trigger[0] //IIS Initialize if(fs==44100) //11.2896MHz(256fs) rIISPSR = (2<<5) + 2; //Prescaler A,B=2 <- FCLK 135.4752MHz(1:2:4) else //fs=22050, 5.6448MHz(256fs) rIISPSR = (5<<5) + 5; //Prescaler A,B=5 <- FCLK 135.4752MHz(1:2:4) rIISCON = (1<<5) + (1<<2) + (1<<1); //Tx DMA enable[5], Rx idle[2], Prescaler enable[1] //Master mode[8],Tx mode[7:6],Low for Left Channel[5],IIS format[4],16bit ch.[3],CDCLK 256fs[2],IISCLK 32fs[1:0] rIISMOD = (0<<8) + (2<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0); rIISFCON = (1<<15) + (1<<13); //Tx DMA,Tx FIFO --> start piling.... puts("Press 'q' to exit!\n"); puts("Press '+' to increase volume, '-' to decrease volume, 'm' to mute or unmute, 'p' to pause or resume\n"); //IIS Tx Start rIISCON |= 0x1; //IIS Interface start while(1) { U8 key = getkey(); if(key=='q'||key=='Q') break; if(key=='+') AdjVolume(0); if(key=='-') AdjVolume(1); if(key=='m'||key=='M') Muting(); if(key=='p'||key=='P') PlayPause(); if((rDSTAT2 & 0xfffff) < (size/6)) ChangeDMA2(); } // { // if((rDSTAT2 & 0xfffff) < (size/6)) // ChangeDMA2(); // } //IIS Tx Stop Delay(10); //For end of H/W Tx rIISCON = 0x0; //IIS Interface stop rDMASKTRIG2 = (1<<2); //DMA2 stop rIISFCON = 0x0; //For FIFO flush size = 0; rGPBCON = save_B; rGPECON = save_E; rGPBUP = save_PB; rGPEUP = save_PE; DisableIrq(BIT_DMA2);//rINTMSK = (BIT_DMA2 | BIT_EINT0); ChangeMPllValue(112, 4, 1); // FCLK=202.8MHz Uart_Init(0, 115200); mute = 1; } //**************** [ Record_Iis ] *************************************** void Record_Iis(void) { unsigned int save_B, save_E, save_PB, save_PE; Uart_TxEmpty(0); ChangeClockDivider(1,1); //1:2:4 ChangeMPllValue(0x96,0x5,0x1); //FCLK=135428571Hz, PCLK=3.385714MHz, 33.857142MHz Uart_Init(33857142,115200); Uart_Printf("[ Record test using UDA1341 ]\n"); save_B = rGPBCON; save_E = rGPECON; save_PB = rGPBUP; save_PE = rGPEUP; IIS_PortSetting(); //Record Buf initialize, Non-cacheable area = 0x31000000 ~ 0x33feffff rec_buf = (unsigned short *)0x31000000; pISR_DMA2 = (unsigned)DMA2_Rec_Done; pISR_EINT0 = (unsigned)Muting; rINTMSK = ~(BIT_DMA2); Init1341(RECORD); //--- DMA2 Initialize rDISRCC2 = (1<<1) + (1<<0); //APB, Fix rDISRC2 = ((U32)IISFIFO); //IISFIFO rDIDSTC2 = (0<<1) + (0<<0); //PHB, Increment rDIDST2 = (int)rec_buf; //0x31000000 ~ rDCON2 = (1<<31)+(0<<30)+(1<<29)+(0<<28)+(0<<27)+(1<<24)+(1<<23)+(1<<22)+(1<<20)+REC_LEN; //Handshake, sync PCLK, TC int, single tx, single service, I2SSDI, I2S Rx request, //Off-reload, half-word, 0x50000 half word. rDMASKTRIG2 = (0<<2) + (1<<1) + 0; //No-stop, DMA2 channel on, No-sw trigger //IIS Initialize //Master,Rx,L-ch=low,IIS,16bit ch,CDCLK=256fs,IISCLK=32fs rIISMOD = (0<<8) + (1<<6) + (0<<5) + (0<<4) + (1<<3) + (0<<2) + (1<<0); rIISPSR = (2<<5) + 2; //Prescaler_A/B=2 <- FCLK 135.4752MHz(1:2:4),11.2896MHz(