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《CY15B104Q芯片详解——基于Cypress数据手册》 CY15B104Q是一款由Cypress Semiconductor公司推出的高速、低功耗的存储器芯片，广泛应用于各种电子设备中，如嵌入式系统、物联网设备、消费类电子产品等。这款芯片以其高效能和可靠性在业界获得了较高的认可度。本文将基于CY15B104Q的数据手册，深入探讨其主要特性和应用。 CY15B104Q是一款串行EEPROM（Electrically Erasable Programmable Read-Only Memory）芯片，它具有非易失性存储的特点，即使在断电的情况下也能保持数据。这种特性使得它在需要长期保存配置信息或固件更新的应用中非常实用。在性能方面，CY15B104Q提供高速的I2C接口，支持多种工作模式，包括快速模式（Fast Mode）和快速模式Plus（Fast Mode Plus），最高数据传输速率可达3.4MHz。这样的高速性能使得它在数据交换密集型的应用中表现出色。在功耗方面，CY15B104Q设计有低功耗模式，可以在待机时大幅度降低电流消耗，从而延长设备的电池寿命。同时，该芯片还支持突发读写操作，能够在短时间内处理大量数据，提高效率的同时也减少了能量损耗。在耐用性上，CY15B104Q具有超过10万次的擦写周期，确保了数据的长期稳定性。此外，其工作电压范围宽，从2.5V到5.5V，兼容性强，可以适应各种电源环境。数据手册中还会详细介绍CY15B104Q的电气特性、引脚定义、操作指令集以及编程指南等内容。例如，它有8个引脚，每个引脚都有特定的功能，如SDA（Serial Data）、SCL（Serial Clock）用于I2C通信，VCC和GND提供电源，以及WP（Write Protect）用于防止意外写入等。此外，CY15B104Q还支持硬件地址锁定功能，允许用户通过硬件跳线或外部电路来固定芯片的I2C地址，避免地址冲突。这在多设备并存的系统中尤其重要。 CY15B104Q是电子设计工程师在构建需要高效、低功耗存储解决方案的项目时，一个值得考虑的选择。通过详细阅读并理解CY15B104Q的数据手册，开发者可以充分利用这款芯片的优势，优化系统设计，提升产品的性能和可靠性。而"excited5ps"可能是指这款芯片在特定应用场景下表现出的卓越性能，可能是在高速数据传输或低功耗模式下的优秀表现。 CY15B104Q芯片结合了高速、低功耗和高耐用性等优点，适用于各种对数据存储和传输有高要求的电子设备。对于想要深入了解这款芯片的工程师，"CY15B104Q.pdf"数据手册无疑是获取详细信息和设计指导的重要资源。

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CY15B104Q.zip （1个子文件）

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CY15B104Q

4-Mbit (512 K × 8) Serial (SPI) F-RAM

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-94240 Rev. *D Revised April 18, 2017

4-Mbit (512 K × 8) Serial (SPI) F-RAM

Features

■ 4-Mbit ferroelectric random access memory (F-RAM) logically

organized as 512 K × 8

❐ High-endurance 100 trillion (10

) read/writes

❐ 151-year data retention (See the Data Retention and

Endurance table)

❐ NoDelay™ writes

❐ Advanced high-reliability ferroelectric process

■ Very fast serial peripheral interface (SPI)

❐ Up to 40-MHz frequency

❐ Direct hardware replacement for serial flash and EEPROM

❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1)

■ Sophisticated write protection scheme

❐ Hardware protection using the Write Protect (WP) pin

❐ Software protection using Write Disable instruction

❐ Software block protection for 1/4, 1/2, or entire array

■ Device ID

❐ Manufacturer ID and Product ID

■ Low power consumption

❐ 300 A active current at 1 MHz

❐ 100 A (typ) standby current

❐ 3 A (typ) sleep mode current

■ Low-voltage operation: V

= 2.0 V to 3.6 V

■ Industrial temperature: –40 C to +85 C

■ Packages

❐ 8-pin small outline integrated circuit (SOIC) package

❐ 8-pin thin dual flat no leads (TDFN) package

■ Restriction of hazardous substances (RoHS) compliant

Functional Description

The CY15B104Q is a 4-Mbit nonvolatile memory employing an

advanced ferroelectric process. A ferroelectric random access

memory or F-RAM is nonvolatile and performs reads and writes

similar to a RAM. It provides reliable data retention for 151 years

while eliminating the complexities, overhead, and system-level

reliability problems caused by serial flash, EEPROM, and other

nonvolatile memories.

Unlike serial flash and EEPROM, the CY15B104Q performs

write operations at bus speed. No write delays are incurred. Data

is written to the memory array immediately after each byte is

successfully transferred to the device. The next bus cycle can

commence without the need for data polling. In addition, the

product offers substantial write endurance compared to other

nonvolatile memories. The CY15B104Q is capable of supporting

read/write cycles, or 100 million times more write cycles

than EEPROM.

These capabilities make the CY15B104Q ideal for nonvolatile

memory applications, requiring frequent or rapid writes.

Examples range from data collection, where the number of write

cycles may be critical, to demanding industrial controls where the

long write time of serial flash or EEPROM can cause data loss.

The CY15B104Q provides substantial benefits to users of serial

EEPROM or flash as a hardware drop-in replacement. The

CY15B104Q uses the high-speed SPI bus, which enhances the

high-speed write capability of F-RAM technology. The device

incorporates a read-only Device ID that allows the host to

determine the manufacturer, product density, and product

revision. The device specifications are guaranteed over an

industrial temperature range of –40 C to +85 C.

For a complete list of related documentation, click here.

Logic Block Diagram

Instruction Decoder

Clock Generator

Control Logic

Write Protect

Instruction Register

Address Register

Counter

512 K x 8

F-RAM Array

Data I/ O Register

Nonvolatile Status

HOLD

SCK

SOSI

Document Number: 001-94240 Rev. *D Page 2 of 22

CY15B104Q

Contents

Pinouts ..............................................................................3

Pin Definitions ..................................................................3

Overview ............................................................................4

Memory Architecture ...................................................4

Serial Peripheral Interface (SPI) Bus ..........................4

SPI Overview ...............................................................4

SPI Modes ...................................................................5

Power Up to First Access ............................................6

Command Structure ....................................................6

WREN - Set Write Enable Latch .................................6

WRDI - Reset Write Enable Latch ...............................6

Status Register and Write Protection .............................7

Read Status Register (RDSR) .....................................7

Write Status Register (WRSR) ....................................7

Memory Operation ............................................................8

Write Operation ...........................................................8

Read Operation ...........................................................8

Fast Read Operation ...................................................8

HOLD Pin Operation .................................................10

Sleep Mode ...............................................................10

Device ID ...................................................................11

Endurance .................................................................11

Maximum Ratings ...........................................................12

Operating Range .............................................................12

DC Electrical Characteristics ........................................12

Data Retention and Endurance .....................................13

Capacitance ....................................................................13

Thermal Resistance ........................................................13

AC Test Conditions ........................................................13

AC Switching Characteristics .......................................14

Power Cycle Timing .......................................................16

Ordering Information ......................................................17

Ordering Code Definitions .........................................17

Package Diagrams ..........................................................18

Acronyms ........................................................................20

Document Conventions .................................................20

Units of Measure .......................................................20

Document History Page .................................................21

Sales, Solutions, and Legal Information ......................22

Worldwide Sales and Design Support ....................... 22

Products ....................................................................22

PSoC® Solutions ......................................................22

Cypress Developer Community .................................22

Technical Support .....................................................22

Document Number: 001-94240 Rev. *D Page 3 of 22

CY15B104Q

Pinouts

Figure 1. 8-pin SOIC Pinout

Figure 2. 8-pin TDFN Pinout

HOLD

SCK

Top View

not to scale

SCK

HOLD

PAD

EXPOSED

Top View

not to scale

Pin Definitions

Pin Name I/O Type Description

Input Chip Select. This active LOW input activates the device. When HIGH, the device enters low-power

standby mode, ignores other inputs, and the output is tristated. When LOW, the device internally

activates the SCK signal. A falling edge on CS must occur before every opcode.

SCK Input Serial Clock. All I/O activity is synchronized to the serial clock. Inputs are latched on the rising

edge and outputs occur on the falling edge. Because the device is synchronous, the clock

frequency may be any value between 0 and 40 MHz and may be interrupted at any time.

[1]

Input Serial Input. All data is input to the device on this pin. The pin is sampled on the rising edge of

SCK and is ignored at other times. It should always be driven to a valid logic level to meet IDD

specifications.

[1]

Output Serial Output. This is the data output pin. It is driven during a read and remains tristated at all

other times including when HOLD

is LOW. Data transitions are driven on the falling edge of the

serial clock.

Input Write Protect. This Active LOW pin prevents write operation to the Status Register when WPEN

is set to ‘1’. This is critical because other write protection features are controlled through the Status

Protection on page 7. This pin must be tied to V

if not used.

HOLD

Input HOLD Pin. The HOLD pin is used when the host CPU must interrupt a memory operation for

another task. When HOLD

is LOW, the current operation is suspended. The device ignores any

transition on SCK or CS

. All transitions on HOLD must occur while SCK is LOW. This pin must be

tied to V

if not used.

Power supply Ground for the device. Must be connected to the ground of the system.

Power supply Power supply input to the device.

EXPOSED PAD No connect The EXPOSED PAD on the bottom of 8-pin TDFN package is not connected to the die. The

EXPOSED PAD should be left floating.

Note

1. SI may be connected to SO for a single pin data interface

Document Number: 001-94240 Rev. *D Page 4 of 22

CY15B104Q

Overview

The CY15B104Q is a serial F-RAM memory. The memory array

is logically organized as 524,288 × 8 bits and is accessed using

an industry-standard serial peripheral interface (SPI) bus. The

functional operation of the F-RAM is similar to serial flash and

serial EEPROMs. The major difference between the

CY15B104Q and a serial flash or EEPROM with the same pinout

is the F-RAM's superior write performance, high endurance, and

low power consumption.

Memory Architecture

When accessing the CY15B104Q, the user addresses 512K

locations of eight data bits each. These eight data bits are shifted

in or out serially. The addresses are accessed using the SPI

protocol, which includes a chip select (to permit multiple devices

on the bus), an opcode, and a three-byte address. The upper 5

bits of the address range are 'don't care' values. The complete

address of 19 bits specifies each byte address uniquely.

Most functions of the CY15B104Q are either controlled by the

SPI interface or handled by on-board circuitry. The access time

for the memory operation is essentially zero, beyond the time

needed for the serial protocol. That is, the memory is read or

written at the speed of the SPI bus. Unlike a serial flash or

EEPROM, it is not necessary to poll the device for a ready

condition because writes occur at bus speed. By the time a new

bus transaction can be shifted into the device, a write operation

is complete. This is explained in more detail in the interface

section.

Serial Peripheral Interface (SPI) Bus

The CY15B104Q is an SPI slave device and operates at speeds

up to 40 MHz. This high-speed serial bus provides high-perfor-

mance serial communication to an SPI master. Many common

microcontrollers have hardware SPI ports allowing a direct

interface. It is simple to emulate the port using ordinary port pins

for microcontrollers that do not. The CY15B104Q operates in SPI

Mode 0 and 3.

SPI Overview

The SPI is a four-pin interface with Chip Select (CS), Serial Input

(SI), Serial Output (SO), and Serial Clock (SCK) pins.

The SPI is a synchronous serial interface, which uses clock and

data pins for memory access and supports multiple devices on

the data bus. A device on the SPI bus is activated using the CS

pin.

The relationship between chip select, clock, and data is dictated

by the SPI mode. This device supports SPI modes 0 and 3. In

both of these modes, data is clocked into the F-RAM on the rising

edge of SCK starting from the first rising edge after CS

goes

active.

The SPI protocol is controlled by opcodes. These opcodes

specify the commands from the bus master to the slave device.

After CS

is activated, the first byte transferred from the bus

master is the opcode. Following the opcode, any addresses and

data are then transferred. The CS

must go inactive after an

operation is complete and before a new opcode can be issued.

The commonly used terms in the SPI protocol are as follows:

SPI Master

The SPI master device controls the operations on the SPI bus.

An SPI bus may have only one master with one or more slave

devices. All the slaves share the same SPI bus lines and the

master may select any of the slave devices using the CS

pin. All

of the operations must be initiated by the master activating a

slave device by pulling the CS

pin of the slave LOW. The master

also generates the SCK and all the data transmission on SI and

SO lines are synchronized with this clock.

SPI Slave

The SPI slave device is activated by the master through the Chip

Select line. A slave device gets the SCK as an input from the SPI

master and all the communication is synchronized with this

clock. An SPI slave never initiates a communication on the SPI

bus and acts only on the instruction from the master.

The CY15B104Q operates as an SPI slave and may share the

SPI bus with other SPI slave devices.

Chip Select (CS

)

To select any slave device, the master needs to pull down the

corresponding CS

pin. Any instruction can be issued to a slave

device only while the CS

pin is LOW. When the device is not

selected, data through the SI pin is ignored and the serial output

pin (SO) remains in a high-impedance state.

Note A new instruction must begin with the falling edge of CS

Therefore, only one opcode can be issued for each active Chip

Select cycle.

Serial Clock (SCK)

The serial clock is generated by the SPI master and the commu-

nication is synchronized with this clock after CS

goes LOW.

The CY15B104Q enables SPI modes 0 and 3 for data commu-

nication. In both of these modes, the inputs are latched by the

slave device on the rising edge of SCK and outputs are issued

on the falling edge. Therefore, the first rising edge of SCK

signifies the arrival of the first Most Significant Bit (MSB) of an

SPI instruction on the SI pin. Further, all data inputs and outputs

are synchronized with SCK.

Data Transmission (SI/SO)

The SPI data bus consists of two lines, SI and SO, for serial data

communication. SI is also referred to as Master Out Slave In

(MOSI) and SO is referred to as Master In Slave Out (MISO). The

master issues instructions to the slave through the SI pin, while

the slave responds through the SO pin. Multiple slave devices

may share the SI and SO lines as described earlier.

The CY15B104Q has two separate pins for SI and SO, which can

be connected with the master as shown in Figure 3.

Document Number: 001-94240 Rev. *D Page 5 of 22

CY15B104Q

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD

and WP pins.

Figure 4 shows such a configuration, which uses only three pins.

Most Significant Bit (MSB)

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

The 4-Mbit serial F-RAM requires a 3-byte address for any read

or write operation. Because the address is only 19 bits, the first

five bits, which are fed in are ignored by the device. Although

these five bits are ‘don’t care’, Cypress recommends that these

bits be set to 0s to enable seamless transition to higher memory

densities.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

CY15B104Q uses the standard opcodes for memory accesses.

Invalid Opcode

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

Status Register

CY15B104Q has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

SPI Modes

CY15B104Q may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS

goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

The two SPI modes are shown in Figure 5 and Figure 6 on page

6. The status of the clock when the bus master is not transferring

data is:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

The device detects the SPI mode from the status of the SCK pin

when the device is selected by bringing the CS

pin LOW. If the

Figure 3. System Configuration with SPI Port

CS1

CS2

HOLD1

HOLD2

CY15B104Q CY15B104Q

WP1

WP2

SCK

SI SO

SCK

HOLD WP

SCK

MOSI

MISO

SPI

Microcontroller

Figure 4. System Configuration without SPI Port

CY15B104Q

Microcontroller

SCK

SI SO

HOLD WP

P1.2

P1.1

P1.0

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