#include "io430.h"
#include "OLED_I2C.h"
#include "delay.h"
void SystemInit();
void GPIO_graceInit();
void BCSplus_graceInit();
void USCI_A0_graceInit();
void USCI_B0_graceInit();
void Timer0_A3_graceInit();
void Timer1_A3_graceInit();
void WDTplus_graceInit();
extern void OLED_Init(void);
//unsigned char *PTxData = (unsigned char *)TxData; // Pointer to TX data array
//unsigned char TXByteCtr = sizeof TxData; // TX byte count
unsigned char i;
int main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;
extern const unsigned char BMP1[];
SystemInit();
DelayInit();
OLED_Init();
while(1)
{
OLED_Fill(0xFF);//全屏点亮
DelayS(2);
OLED_Fill(0x00);//全屏灭
DelayS(2);
for(i=0;i<5;i++)
{
OLED_ShowCN(22+i*16,0,i);//测试显示中文
}
DelayS(2);
OLED_ShowStr(0,3,"Hello World !",1);//测试6*8字符
OLED_ShowStr(0,4,"Hello World !",2);//测试8*16字符
DelayS(2);
OLED_OFF();//测试OLED休眠
DelayS(2);
OLED_ON();//测试OLED休眠后唤醒
DelayS(2);
OLED_DrawBMP(0,0,128,8,(unsigned char *)BMP1);//测试BMP位图显示
DelayS(2);
OLED_CLS();//清屏
}
}
void SystemInit()
{
do
{
// Clear OSC fault flag
IFG1 &= ~OFIFG;
// 50us delay
__delay_cycles(50);
} while (IFG1 & OFIFG);
/*
* IFG2, Interrupt Flag Register 2
*
* UCB0TXIFG -- Interrupt pending
* UCB0RXIFG -- Interrupt pending
* ~UCA0TXIFG -- No interrupt pending
* UCA0RXIFG -- Interrupt pending
*
* Note: ~UCA0TXIFG indicates that UCA0TXIFG has value zero
*/
IFG2 &= ~(UCB0TXIFG | UCB0RXIFG | UCA0RXIFG);
/*
* IE2, Interrupt Enable Register 2
*
* UCB0TXIE -- Interrupt enabled
* UCB0RXIE -- Interrupt enabled
* ~UCA0TXIE -- Interrupt disabled
* UCA0RXIE -- Interrupt enabled
*
* Note: ~UCA0TXIE indicates that UCA0TXIE has value zero
*/
// IE2 |= UCB0TXIE | UCB0RXIE | UCA0RXIE;
IE2 |= UCB0TXIE | UCB0RXIE;
/*
* SR, Status Register
*
* ~SCG1 -- Disable System clock generator 1
* ~SCG0 -- Disable System clock generator 0
* ~OSCOFF -- Oscillator On
* ~CPUOFF -- CPU On
* GIE -- General interrupt enable
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
__bis_SR_register(GIE);
/* USER CODE START (section: System_graceInit_epilogue) */
/* User code */
/* Stop watchdog timer from timing out during initial start-up. */
WDTCTL = WDTPW | WDTHOLD;
/* initialize Config for the MSP430 GPIO */
GPIO_graceInit();
/* initialize Config for the MSP430 2xx family clock systems (BCS) */
BCSplus_graceInit();
/* initialize Config for the MSP430 USCI_A0 */
USCI_A0_graceInit();
/* initialize Config for the MSP430 USCI_B0 */
USCI_B0_graceInit();
/* initialize Config for the MSP430 A3 Timer0 */
Timer0_A3_graceInit();
/* initialize Config for the MSP430 A3 Timer0 */
Timer1_A3_graceInit();
/* initialize Config for the MSP430 WDT+ */
WDTplus_graceInit();
}
void GPIO_graceInit(void)
{
/* USER CODE START (section: GPIO_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: GPIO_graceInit_prologue) */
/* Port 1 Port Select 2 Register */
P1SEL2 = BIT1 | BIT2 | BIT6 | BIT7;
/* Port 1 Output Register */
P1OUT = 0;
/* Port 1 Port Select Register */
P1SEL = BIT1 | BIT2 | BIT6 | BIT7;
/* Port 1 Direction Register */
P1DIR = BIT3;
/* Port 1 Interrupt Edge Select Register */
P1IES = 0;
/* Port 1 Interrupt Flag Register */
P1IFG = 0;
/* Port 2 Output Register */
P2OUT = 0;
/* Port 2 Direction Register */
P2DIR = 0;
/* Port 2 Interrupt Edge Select Register */
P2IES = 0;
/* Port 2 Interrupt Flag Register */
P2IFG = 0;
/* Port 3 Output Register */
P3OUT = 0;
/* Port 3 Direction Register */
P3DIR = 0;
/* USER CODE START (section: GPIO_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: GPIO_graceInit_epilogue) */
}
void BCSplus_graceInit(void)
{
/* USER CODE START (section: BCSplus_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: BCSplus_graceInit_prologue) */
/*
* Basic Clock System Control 2
*
* SELM_0 -- DCOCLK
* DIVM_0 -- Divide by 1
* ~SELS -- DCOCLK
* DIVS_0 -- Divide by 1
* ~DCOR -- DCO uses internal resistor
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
BCSCTL2 = SELM_0 | DIVM_0 | DIVS_0;
if (CALBC1_1MHZ != 0xFF) {
/* Follow recommended flow. First, clear all DCOx and MODx bits. Then
* apply new RSELx values. Finally, apply new DCOx and MODx bit values.
*/
DCOCTL = 0x00;
BCSCTL1 = CALBC1_1MHZ; /* Set DCO to 1MHz */
DCOCTL = CALDCO_1MHZ;
}
/*
* Basic Clock System Control 1
*
* XT2OFF -- Disable XT2CLK
* ~XTS -- Low Frequency
* DIVA_0 -- Divide by 1
*
* Note: ~XTS indicates that XTS has value zero
*/
BCSCTL1 |= XT2OFF | DIVA_0;
/*
* Basic Clock System Control 3
*
* XT2S_0 -- 0.4 - 1 MHz
* LFXT1S_0 -- If XTS = 0, XT1 = 32768kHz Crystal ; If XTS = 1, XT1 = 0.4 - 1-MHz crystal or resonator
* XCAP_1 -- ~6 pF
*/
BCSCTL3 = XT2S_0 | LFXT1S_2 | XCAP_1;
/* USER CODE START (section: BCSplus_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: BCSplus_graceInit_epilogue) */
}
void USCI_A0_graceInit(void)
{
/* USER CODE START (section: USCI_A0_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: USCI_A0_graceInit_prologue) */
/* Disable USCI */
UCA0CTL1 |= UCSWRST;
/*
* Control Register 1
*
* UCSSEL_2 -- SMCLK
* ~UCRXEIE -- Erroneous characters rejected and UCAxRXIFG is not set
* ~UCBRKIE -- Received break characters do not set UCAxRXIFG
* ~UCDORM -- Not dormant. All received characters will set UCAxRXIFG
* ~UCTXADDR -- Next frame transmitted is data
* ~UCTXBRK -- Next frame transmitted is not a break
* UCSWRST -- Enabled. USCI logic held in reset state
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCA0CTL1 = UCSSEL_2 | UCSWRST;
/*
* Modulation Control Register
*
* UCBRF_0 -- First stage 0
* UCBRS_1 -- Second stage 1
* ~UCOS16 -- Disabled
*
* Note: ~UCOS16 indicates that UCOS16 has value zero
*/
UCA0MCTL = UCBRF_0 | UCBRS_1;
/* Baud rate control register 0 */
UCA0BR0 = 104;
/* Enable USCI */
UCA0CTL1 &= ~UCSWRST;
/* USER CODE START (section: USCI_A0_graceInit_epilogue) */
/* User code */
/* USER CODE END (section: USCI_A0_graceInit_epilogue) */
}
void USCI_B0_graceInit(void)
{
/* USER CODE START (section: USCI_B0_graceInit_prologue) */
/* User initialization code */
/* USER CODE END (section: USCI_B0_graceInit_prologue) */
/* Disable USCI */
UCB0CTL1 |= UCSWRST;
/*
* Control Register 0
*
* ~UCA10 -- Own address is a 7-bit address
* ~UCSLA10 -- Address slave with 7-bit address
* ~UCMM -- Single master environment. There is no other master in the system. The address compare unit is disabled
* UCMST -- Master mode
* UCMODE_3 -- I2C Mode
* UCSYNC -- Synchronous Mode
*
* Note: ~<BIT> indicates that <BIT> has value zero
*/
UCB0CTL0 = UCMST | UCMODE_3 | UCSYNC;
/
