7 Series FPGAs
Memory Resources
User Guide
UG473 (v1.7) October 2, 2012
7 Series FPGAs Memory Resources www.xilinx.com UG473 (v1.7) October 2, 2012
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Revision History
The following table shows the revision history for this document.
Date Version Revision
03/01/11 1.0 Initial Xilinx release.
03/28/11 1.1 Updated disclaimer and copyright on page 2.
Updated values in Table 2-1, descriptions in Table 2-3, and values in Table 2-4. Modified
discussions in Almost Empty Flag, Full Flag, and Almost Full Flag sections. Updated
values in Table 2-7 and Table 2-8. Revised Figure 2-6. Revised discussion of clock event
2 and clock event 4 on page 57. Updated Case 3: Reading from a Full FIFO including
Figure 2-8.
04/14/11 1.2 Added 7 Series FPGAs Block RAM and FIFO Differences from Previous FPGA
Generations. Added Table 1-2: Block RAM Resources in 7 Series Devices. Clarified valid
values for Read Width - READ_WIDTH_[A|B] and Write Width -
WRITE_WIDTH_[A|B] Updated the example in Block RAM Location Constraints.
Updated parameter names in Table 1-18.
Clarified the flag behavior in the Synchronous FIFO introduction. Revised the FIFO
Almost Full/Empty Flag Offset Range section including adding Note 1 to Table 2-8,
removing Equation 2-1 and revising Equation 2-2 to be the new Equation 2-1.
Updated port connection instructions for WEBWE[7:0].
10/18/11 1.3 Added Stacked Silicon Interconnect. Added Artix-7 and Virtex-7 families to Table 1-2
and updated table notes.
11/18/11 1.4 Updated second bullet in Changes from Virtex-6 FPGAs.
UG473 (v1.7) October 2, 2012 www.xilinx.com 7 Series FPGAs Memory Resources
01/30/12 1.5 In Table 1-2, removed XC7A8, XC7A15, XC7A30T, and XC7A50T; updated number of
36 Kb block RAM blocks per column for XC7K420T and XC7VX550T; updated note 1 to
say “GTP/GTX Quad.”
Updated Simple Dual-Port Block RAM.
07/04/12 1.6 Updated fifth and sixth bullets in Changes from Virtex-6 FPGAs.
Added Virtex-7 devices to Table 1-2. Updated descriptions of RAMB36E1, RAMB18E1,
and FIFO18E1 in Table 1-6.
Updated description of WREN in Table 2-3. In Table 2-9, replaced T
RCCK_RST
/T
RCKC_RST
with T
RREC_RST
/T
RREM_RST
.
10/02/12 1.7 Removed XC7A350T, XC7V1500T, and XC7VH290T from Table 1-2.
Date Version Revision
7 Series FPGAs Memory Resources www.xilinx.com 5
UG473 (v1.7) October 2, 2012
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Preface: About This Guide
Guide Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7 Series FPGAs Block RAM and FIFO Differences from Previous FPGA Generations 9
Changes from Virtex-6 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Changes from Spartan-6 FPGAs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Additional Support Resources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 1: Block RAM Resources
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block RAM Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Synchronous Dual-Port and Single-Port RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Write Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
WRITE_FIRST or Transparent Mode (Default). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
READ_FIRST or Read-Before-Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
NO_CHANGE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Conflict Avoidance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Asynchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Synchronous Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Additional Block RAM Features in 7 Series Devices . . . . . . . . . . . . . . . . . . . . . . . . . 19
Optional Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Independent Read and Write Port Width Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Simple Dual-Port Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Cascadable Block RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Byte-Wide Write Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Block RAM Error Correction Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power Gating of Unused Block RAMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block RAM Library Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Block RAM Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Clock - CLKARDCLK and CLKBWRCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Enable - ENARDEN and ENBWREN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Byte-Wide Write Enable - WEA and WEBWE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Register Enable - REGCEA, REGCE, and REGCEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Set/Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
RSTREGARSTREG, RSTREGB, RSTRAMARSTRAM, and RSTRAMB. . . . . . . . . . . . . . 27
Address Bus - ADDRARDADDR and ADDRBWRADDR . . . . . . . . . . . . . . . . . . . . . . 27
Data-In Buses - DIADI, DIPADIP, DIBDI, and DIPBDIP. . . . . . . . . . . . . . . . . . . . . . . . 29
Data-Out Buses - DOADO, DOPADOP, DOBDO, and DOPBDOP . . . . . . . . . . . . . . . 29
Cascade In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
CASCADEINA, CASCADEINB, CASCADEOUTA, and CASCADEOUTB . . . . . . . . . . 29
Inverting Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table of Contents
