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Application Note: QAN20
Digital UART Design in HDL
Thomas Oelsner
QuickLogic Europe
Introduction
The use of hardware description language (HDL) is becoming a more dominant factor, when designing
and verifying FPGA designs. The use of behavior level description not only increases the design
productivity, but also provides unique advantages in the design verification. The most dominant HDLs
today are called Verilog and VHDL. This application note will illustrate the use of Verilog in design and
verification of a digital UART (
U
niversal
A
synchronous
R
eceiver &
T
ransmitter).
Defining the UART.
The UART consists of two independent HDL
modules. One module implements the
transmitter, while the other module implements
the receiver. The transmitter and receiver
modules can be combined at the top level of the
design, for any combinations of transmitter and
receiver channels required. Data can be written
to the transmitter and read out from the receiver,
all through a single 8 bit bi-directional CPU
interface. Address mapping for the transmitter
and receiver channels can easily be build into
the interface at the top level of the design. Both
modules share a common master clock called
mclkx16. Within each module mclkx16 are
divided down to independent baudrate clocks.
parityerr
framingerr
overrun
mclkx16
reset
read
data[7:0]
rx
rxrdy
write
tx
txrdy
Fig. 1 Digital UART
