MAC_Transceiver.rar_Embedded Ethernet_FPGA 网口_MAC VHDL_data li

#-- Synopsys, Inc. #-- Version 9.6.2 #-- Project file D:\XilinxProjects\MAC_Verilog\run_options.txt #-- Written on Tue Nov 10 14:41:19 2009 #add_file options add_file -verilog "./eth_txstatem.v" add_file -verilog "./eth_txcounters.v" add_file -verilog "./eth_transmitcontrol.v" add_file -verilog "./eth_spram_256x32.v" add_file -verilog "./eth_shiftreg.v" add_file -verilog "./eth_rxstatem.v" add_file -verilog "./eth_rxcounters.v" add_file -verilog "./eth_rxaddrcheck.v" add_file -verilog "./eth_register.v" add_file -verilog "./eth_receivecontrol.v" add_file -verilog "./eth_random.v" add_file -verilog "./eth_outputcontrol.v" add_file -verilog "./eth_fifo.v" add_file -verilog "./eth_crc.v" add_file -verilog "./eth_clockgen.v" add_file -verilog "./eth_wishbone.v" add_file -verilog "./eth_txethmac.v" add_file -verilog "./eth_rxethmac.v" add_file -verilog "./eth_registers.v" add_file -verilog "./eth_miim.v" add_file -verilog "./eth_macstatus.v" add_file -verilog "./eth_maccontrol.v" add_file -verilog "./eth_top.v" add_file -constraint "D:/XilinxProjects/MAC_Verilog/eth_top.sdc" #implementation: "MAC_Verilog" impl -add MAC_Verilog -type fpga #device options set_option -technology VIRTEX4 set_option -part xc4vlx15 set_option -package sf363 set_option -speed_grade -12 set_option -part_companion "" #compilation/mapping options set_option -default_enum_encoding default set_option -resource_sharing 1 set_option -use_fsm_explorer 0 set_option -top_module "eth_top" #map options set_option -frequency auto set_option -vendor_xcompatible_mode 0 set_option -vendor_xcompatible_mode 0 set_option -run_prop_extract 1 set_option -fanout_limit 100 set_option -disable_io_insertion 0 set_option -pipe 1 set_option -update_models_cp 0 set_option -verification_mode 0 set_option -retiming 0 set_option -no_sequential_opt 0 set_option -fixgatedclocks 3 set_option -fixgeneratedclocks 3 #sequential_optimizations options set_option -symbolic_fsm_compiler 1 #simulation options set_option -write_verilog 0 set_option -write_vhdl 0 #VIF options set_option -write_vif 1 #automatic place and route (vendor) options set_option -write_apr_constraint 1 #set result format/file last project -result_file "./eth_top.edn" # #implementation attributes set_option -vlog_std v2001 set_option -num_critical_paths 0 set_option -num_startend_points 0 impl -active "MAC_Verilog"