vhdl-code.vhd.rar_code

library IEEE;

use IEEE.STD_LOGIC_1164.all;

package ad_filt is

-- Declare constants

constant NUM_TAPS : integer := 16;

constant mu : integer := 16;

type sh_reg is array (0 to NUM_TAPS-1) of std_logic_vector(15 downto 0);

type tmp_reg is array (0 to NUM_TAPS-1) of std_logic_vector(31 downto 0);

end ad_filt;