mcbsp_loopback.rar_F2812_MCBSP

// // TMDX ALPHA RELEASE // Intended for product evaluation purposes // //########################################################################### // // FILE: Example_28xMCBSP_FFDLB.c // // TITLE: DSP28 Device McBSP Digital Loop Back porgram. // All these tests will self validate the code and update the // Test status in Test_status array. // And PASS_Flag =0xDOBE for pass, 0xDEAD for fail // // Test 1 DLB set, 8-bit word, enable R/Xcompanding u-law , // 14 bitdata, leading LSBs are 00 // Internal clocks, Frame sync on DXR-XSR write // CLKX = LSPCLK/16, CLKGDIV =15, CLKR internal tied to CLKR // // Test 2 DLB set, 16-bit word,Fwidth 8bits, (FSGM has to be 1) // Rjustifed, zero fill,NO R/Xcompanding, // Internal clocks, Frame sync on DXR-XSR write // CLKX = LSPCLK/4, CLKGDIV =3, CLKR internal tied to CLKR // // // //########################################################################### // // Ver | dd mmm yyyy | Who | Description of changes // =====|=============|======|=============================================== // 0.58| 03 July2002 | S.S. | McBSP example //########################################################################### #include "DSP28_Device.h" #include "DSP28_Globalprototypes.h" // Prototype statements for functions found within this file. // interrupt void ISRTimer2(void); void delay_loop(void); void mcbsp_dlb8(void); void mcbsp_dlb16(void); void mcbsp_xmit(int a, int b); void mcbsp_fifo_init(void); void error(int); void program_stop(); unsigned int var1 = 0; unsigned int var2 = 0; unsigned int var3 = 0; unsigned int var4 = 0; unsigned int var5 = 0; unsigned int test_count = 0; unsigned int Test_flag1 = 0; unsigned int Test_flag2 = 0; unsigned int Test_flag3 = 0; unsigned int Test_flag4 = 0; unsigned int Test_var = 0; unsigned int Test_status[32]; unsigned int PASS_flag = 0; void main(void) { // Step 1. Initialize System Control registers, PLL, WatchDog, Clocks to default state: // This function is found in the DSP28_SysCtrl.c file. InitSysCtrl(); // Step 2. Select GPIO for the device or for the specific application: // This function is found in the DSP28_Gpio.c file. // InitGpio(); skip this as this is example selects the I/O for McBSP in this file itself EALLOW; GpioMuxRegs.GPFMUX.all=0x7E00; // Select GPIOs to be McBSP pins // Port F MUX - x111 1110 0000 0000 EDIS; // Step 3. Initialize PIE vector table: // The PIE vector table is initialized with pointers to shell Interrupt // Service Routines (ISR). The shell routines are found in DSP28_DefaultIsr.c. // Insert user specific ISR code in the appropriate shell ISR routine in // the DSP28_DefaultIsr.c file. // Disable and clear all CPU interrupts: DINT; IER = 0x0000; IFR = 0x0000; // Initialize Pie Control Registers To Default State: // This function is found in the DSP28_PieCtrl.c file. InitPieCtrl(); // Initialize the PIE Vector Table To a Known State: // This function is found in DSP28_PieVect.c. // This function populates the PIE vector table with pointers // to the shell ISR functions found in DSP28_DefaultIsr.c. InitPieVectTable(); // Step 4. Initialize all the Device Peripherals to a known state: // This function is found in DSP28_InitPeripherals.c // InitPeripherals(); skip this for GPIO tests // Step 5. User specific functions, Reassign vectors (optional), Enable Interrupts: mcbsp_fifo_init(); // Initialize the Mcbsp FIFO mcbsp_dlb8(); // Digital loop back test mcbsp_dlb16(); // Update Test status if(PASS_flag !=0) PASS_flag=0xDEAD; // Test code exit here.. else PASS_flag=0xD0BE; // Test code exit he // Step 6. IDLE loop. Just sit and loop forever: asm(" ESTOP0"); // Break point for(;;); } // Step 7. Insert all local Interrupt Service Routines (ISRs) and functions here: // If local ISRs are used, reassign vector addresses in vector table as // shown in Step 5 // Some Useful local functions void delay_loop() { long i; for (i = 0; i < 1000000; i++) {} } void error(int ErrorFlag) { PASS_flag =0xDEAD; Test_status[ Test_var]= 0xDEAD; // asm(" ESTOP0"); // Test failed!! Stop! // for (;;); } // Test 1 DLB, 8-bit word, enable R/Xcompanding u-law , // 14 bitdata, leading LSBs are 00 // Internal clocks, Frame sync on DXR-XSR write // CLKX = LSPCLK/16, CLKGDIV =15, CLKR internal tied to CLKR void mcbsp_dlb8() { // McBSP register settings for Digital loop back McbspaRegs.SPCR2.all=0x0000; // XRST =0 McbspaRegs.SPCR1.all=0x8000; // RRST =0, DLB enabled McbspaRegs.RCR2.all=0x0; McbspaRegs.RCR1.all=0x0; McbspaRegs.XCR2.all=0x0; McbspaRegs.XCR1.all=0x0; McbspaRegs.SRGR2.all=0x200f; McbspaRegs.SRGR1.all=0x0001; McbspaRegs.MCR2.all=0x0; McbspaRegs.MCR1.all=0x0; McbspaRegs.PCR1.all=0x00a00; // Bit changes for the test McbspaRegs.SPCR1.bit.RJUST =0; // word McbspaRegs.SRGR2.bit.FSGM=0; // FSGM =0 for FSX based on write to DXR -XSR McbspaRegs.SRGR1.bit.CLKGDV=15; // set CLKGDV = 15 McbspaRegs.RCR2.bit.RCOMPAND =2; // R/XCOMPAND with ulaw McbspaRegs.XCR2.bit.XCOMPAND =2; // R/XCOMPAND with ulaw // McBSP Reset to enable McbspaRegs.SPCR2.bit.XRST =1; // enable XRST/RRST McbspaRegs.SPCR1.bit.RRST=1; delay_loop(); McbspaRegs.SPCR2.all |=0x00C0; // Only enable FRST,GRST used after var1 =0x034c; var2 =0x0; // word to be xmitted mcbsp_xmit(var1,var2); // while(McbspaRegs.SPCR1.bit.RRDY==0) { } // Check for receive while(McbspaRegs.MFFRX.bit.ST==0) { } Test_flag4 = McbspaRegs.DRR1.all; // read DRR1 if(Test_flag4 != 0x034c) error(1); else Test_status[ Test_var]= 0x5000; // update Test_status a test number Test_var++; } // Test 2, DLB, 16-bit word,Fwidth 8bits, (FSGM has to be 1) // Rjustifed, zero fill,NO R/Xcompanding, // internal clocks, Frame sync on DXR-XSR write // CLKX = LSPCLK/4, CLKGDIV =3, CLKR internal tied to CLKR void mcbsp_dlb16() { McbspaRegs.SPCR2.all=0x0000; // XRST =0 McbspaRegs.SPCR1.all=0x8000; // RRST =0, DLB enabled McbspaRegs.RCR2.all=0x0; McbspaRegs.RCR1.all=0x0; McbspaRegs.XCR2.all=0x0; McbspaRegs.XCR1.all=0x0; McbspaRegs.SRGR2.all=0x200f; McbspaRegs.SRGR1.all=0x0001; McbspaRegs.MCR2.all=0x0; McbspaRegs.MCR1.all=0x0; McbspaRegs.PCR1.all=0x00a00; // Bit changes for the test McbspaRegs.SPCR1.bit.RJUST =00; // word Rjustifed McbspaRegs.SRGR2.bit.FSGM=1; // FSGM =1 for FSX based on write to DXR -XSR // has to be set FWID to work! McbspaRegs.SRGR2.bit.FPER=31; // set FPER = 31 McbspaRegs.SRGR1.bit.CLKGDV =3; // set CLKGDV = 3 McbspaRegs.SRGR1.bit.FWID =8; // set Fwidth =8 McbspaRegs.RC