Core name : Xilinx Distributed Memory Generator
Version : v4.1
Release Date: April 24, 2009
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Resolved Issues
4. Known Issues
5. Technical Support
6. Core Release History
========================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this core,
please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator v4.1
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/DIST_MEM_GEN.htm
2. NEW FEATURES
- ISE 11.1 software support
- Virtex-6 and Spartan-6 support
3. RESOLVED ISSUES
4. KNOWN ISSUES
The following are known issues for v3.4 of this core at time of release:
- When a large Distributed Memory Generator IP is generated, CORE
Generator runs out of memory and fails to generate.
- CR 431917
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the release notes Answer Record
for the ISE 10.1i IP Update 1 at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
5. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
6. CORE RELEASE HISTORY
Date By Version Description
========================================================================
04/24/2009 Xilinx, Inc. 4.1 11.1 support; Revised to v4.1; Virtex-6 and Spartan-6 support
03/24/2008 Xilinx, Inc. 3.4 10.1 support; Revised to v3.4.
04/02/2007 Xilinx, Inc. 3.3 9.1i support; Revised to v3.3; Spartan-3AN and Spartan-3A DSP support
09/21/2006 Xilinx, Inc. 3.2 8.2i support; Revised to v3.2; Spartan-3A support
07/13/2006 Xilinx, Inc. 3.1 8.2i support; Revised to v3.1
01/18/2006 Xilinx, Inc. 2.1 8.1i support; Revised to v2.1
04/28/2005 Xilinx, Inc. 1.1 7.1i Service Pack 1 support; First release
========================================================================
(c) Copyright 2005 - 2009 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
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rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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(2) Xilinx shall not be liable (whether in contract or tort,
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cicip1.asy 606B
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Rcosine_ram2048.coe 20KB
Rcosine_ram2048.coe 20KB
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CViewSelector_StrTbl 33B
behavioral.dat 3KB
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cicip2_a.dat 1KB
rom_a.dat 1KB
sc2mult_a.dat 1017B
scmult_a.dat 1014B
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behavioral.dbs 9KB
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behavioral.dbs 4KB
cicip1_a.dbs 2KB
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