AudioVideoConfig.zip_FPGAI2C配置_TapVideoConfig资源-CSDN文库

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AudioVideoConfig.zip （17个子文件）

altera_up_avalon_audio_and_video_config

UP_PTF_Parser.pm 7KB

hdl

Altera_UP_I2C_Auto_Initialize.v 8KB

Altera_UP_I2C.v 9KB

Altera_UP_Avalon_Audio_and_Video_Config.v 8KB

Altera_UP_Slow_Clock_Generator.v 4KB

sdk

alt_up_audio_video_config.c 14KB

alt_up_audio_video_config_regs.h 11KB

alt_up_audio_video_config.h 11KB

UP_HDL_Writer.pm 4KB

UP_IP_Core_Generator.pl 4KB

UP_System_Info.pm 5KB

class.ptf 25KB

UP_HDL_Parser.pm 8KB

doc

ADV7123_a.pdf 365KB

WM8731_WM8731L.pdf 721KB

AudioVideoConfig.pdf 227KB

UP_Extras.pm 4KB

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

ADV7123

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 1998

CMOS, 240 MHz

Triple 10-Bit High Speed Video DAC

FUNCTIONAL BLOCK DIAGRAM

R9–R0

GND

SET

IOR

COMP

ADV7123

REF

VOLTAGE

REFERENCE

CIRCUIT

G9–G0

B9–B0

IOG

IOB

PSAVE

POWER-DOWN

MODE

BLANK

SYNC

CLOCK

DAC10

DATA

DAC10

DATA

DAC10

DATA

BLANK AND

SYNC LOGIC

FEATURES

240 MSPS Throughput Rate

Triple 10-Bit D/A Converters

SFDR

–70 dB at f

CLK

= 50 MHz; f

OUT

= 1 MHz

–53 dB at f

CLK

= 140 MHz; f

OUT

= 40 MHz

RS-343A/RS-170 Compatible Output

Complementary Outputs

DAC Output Current Range 2 mA to 26 mA

TTL-Compatible Inputs

Internal Reference (1.23 V)

Single Supply +5 V/+3.3 V Operation

48-Lead LQFP Package

Low Power Dissipation (30 mW min @ 3 V)

Low Power Standby Mode (6 mW typ @ 3 V)

Industrial Temperature Range (–408C to +858C)

APPLICATIONS

Digital Video Systems (1600 3 1200 @ 100 Hz)

High Resolution Color Graphics

Digital Radio Modulation

Image Processing

Instrumentation

Video Signal Reconstruction

GENERAL DESCRIPTION

The ADV7123 (ADV

) is a triple high speed, digital-to-analog

converter on a single monolithic chip. It consists of three

high speed, 10-bit, video D/A converters with complementary

outputs, a standard TTL input interface and a high impedance,

analog output current source.

The ADV7123 has three separate 10-bit-wide input ports. A

single +5 V/+3.3 V power supply and clock are all that are

required to make the part functional. The ADV7123 has addi-

tional video control signals, composite SYNC and BLANK.

The ADV7123 also has a power-save mode.

The ADV7123 is fabricated in a +5 V CMOS process. Its

monolithic CMOS construction ensures greater functionality

with lower power dissipation. The ADV7123 is available in a

48-lead LQFP package.

PRODUCT HIGHLIGHTS

1. 240 MSPS Throughput.

2. Guaranteed monotonic to 10 bits.

3. Compatible with a wide variety of high resolution color

graphics systems including RS-343A and RS-170A.

ADV is a registered trademark of Analog Devices, Inc.

–2–

REV. A

ADV7123–SPECIFICATIONS

5 V SPECIFICATIONS

Parameter Min Typ Max Units Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits

Integral Nonlinearity (BSL) –1 ±0.4 +1 LSB

Differential Nonlinearity –1 ±0.25 +1 LSB Guaranteed Monotonic

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

Input Low Voltage, V

0.8 V

Input Current, I

–1 +1 µAV

= 0.0 V or V

PSAVE Pull-Up Current 20 µA

Input Capacitance, C

10 pF

ANALOG OUTPUTS

Output Current 2.0 26.5 mA Green DAC, Sync = High

Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low

DAC to DAC Matching 1.0 5 %

Output Compliance Range, V

0 +1.4 V

Output Impedance, R

OUT

100 kΩ

Output Capacitance, C

OUT

10 pF I

OUT

= 0 mA

Offset Error –0.025 +0.025 % FSR Tested with DAC Output = 0 V

Gain Error

–5.0 +5.0 % FSR FSR = 17.62 mA

VOLTAGE REFERENCE (Ext. and Int.)

Reference Range, V

REF

1.12 1.235 1.35 V

POWER DISSIPATION

Digital Supply Current

3.4 9 mA f

CLK

= 50 MHz

Digital Supply Current

10.5 15 mA f

CLK

= 140 MHz

Digital Supply Current

18 25 mA f

CLK

= 240 MHz

Analog Supply Current 67 72 mA R

SET

= 560 Ω

Analog Supply Current 8 mA R

SET

= 4933 Ω

Standby Supply Current

2.1 5.0 mA PSAVE = Low, Digital and Control

Inputs at V

Power Supply Rejection Ratio 0.1 0.5 %/%

NOTES

Temperature range T

MIN

to T

MAX

: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.

Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V

REF

SET

× K × (3FFH) and K = 7.9896.

Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V

These max/min specifications are guaranteed by characterization to be over 4.75 V to 5.25 V range.

Specifications subject to change without notice.

= +5 V 6 5%, V

REF

= 1.235 V, R

SET

= 560 V, C

= 10 pF. All specifications T

MIN

to T

MAX

unless

otherwise noted, T

MAX

= 1108C)

–3–REV. A

ADV7123

3.3 V SPECIFICATIONS

Parameter Min Typ Max Units Test Conditions

STATIC PERFORMANCE

Resolution (Each DAC) 10 Bits R

SET

= 680 Ω

Integral Nonlinearity (BSL) –1 0.5 +1 LSB R

SET

= 680 Ω

Differential Nonlinearity –1 0.25 +1 LSB R

SET

= 680 Ω

DIGITAL AND CONTROL INPUTS

Input High Voltage, V

2.0 V

Input Low Voltage, V

0.8 V

Input Current, I

–1 +1 µAV

= 0.0 V or V

PSAVE Pull-Up Current 20 µA

Input Capacitance, C

10 pF

ANALOG OUTPUTS

Output Current 2.0 26.5 mA Green DAC, Sync = High

Output Current 2.0 18.5 mA R/G/B DAC, Sync = Low

DAC to DAC Matching 1.0 %

Output Compliance Range, V

0 +1.4 V

Output Impedance, R

OUT

70 kΩ

Output Capacitance, C

OUT

10 pF

Offset Error 0 0 % FSR Tested with DAC Output = 0 V

Gain Error

0 % FSR FSR = 17.62 mA

VOLTAGE REFERENCE (Ext.)

Reference Range, V

REF

1.12 1.235 1.35 V

VOLTAGE REFERENCE (Int.)

Reference Range, V

REF

1.235 V

POWER DISSIPATION

Digital Supply Current

2.2 5.0 mA f

CLK

= 50 MHz

Digital Supply Current

6.5 12.0 mA f

CLK

= 140 MHz

Digital Supply Current

11 15 mA f

CLK

= 240 MHz

Analog Supply Current 67 72 mA R

SET

= 560 Ω

Analog Supply Current 8 mA R

SET

= 4933 Ω

Standby Supply Current 2.1 5.0 mA PSAVE = Low, Digital and Control

Inputs at V

Power Supply Rejection Ratio 0.1 0.5 %/%

NOTES

These max/min specifications are guaranteed by characterization to be over 3.0 V to 3.6 V range.

Temperature range T

MIN

to T

MAX

: –40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.

Gain error = (Measured (FSC)/Ideal (FSC) –1) × 100), where Ideal = V

REF

SET

× K × (3FFH) and K = 7.9896.

Digital supply is measured with continuous clock with data input corresponding to a ramp pattern and with an input level at 0 V and V

Specifications subject to change without notice.

= +3.0 V –3.6 V, V

REF

= 1.235 V, R

SET

= 560 V, C

= 10 pF. All specifications T

MIN

to T

MAX

unless

otherwise noted, T

MAX

= 1108C)

–4–

REV. A

ADV7123–SPECIFICATIONS

5 V DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Units

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

Single-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz 67 dBc

CLK

= 50 MHz; f

OUT

= 2.51 MHz 67 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz 63 dBc

CLK

= 50 MHz; f

OUT

= 20.2 MHz 55 dBc

CLK

= 100 MHz; f

OUT

= 2.51 MHz 62 dBc

CLK

= 100 MHz; f

OUT

= 5.04 MHz 60 dBc

CLK

= 100 MHz; f

OUT

= 20.2 MHz 54 dBc

CLK

= 100 MHz; f

OUT

= 40.4 MHz 48 dBc

CLK

= 140 MHz; f

OUT

= 2.51 MHz 57 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz 58 dBc

CLK

= 140 MHz; f

OUT

= 20.2 MHz 52 dBc

CLK

= 140 MHz; f

OUT

= 40.4 MHz 41 dBc

Double-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz 70 dBc

CLK

= 50 MHz; f

OUT

= 2.51 MHz 70 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz 65 dBc

CLK

= 50 MHz; f

OUT

= 20.2 MHz 54 dBc

CLK

= 100 MHz; f

OUT

= 2.51 MHz 67 dBc

CLK

= 100 MHz; f

OUT

= 5.04 MHz 63 dBc

CLK

= 100 MHz; f

OUT

= 20.2 MHz 58 dBc

CLK

= 100 MHz; f

OUT

= 40.4 MHz 52 dBc

CLK

= 140 MHz; f

OUT

= 2.51 MHz 62 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz 61 dBc

CLK

= 140 MHz; f

OUT

= 20.2 MHz 55 dBc

CLK

= 140 MHz; f

OUT

= 40.4 MHz 53 dBc

Spurious-Free Dynamic Range Within a Window

Single-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz; 1 MHz Span 77 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz; 2 MHz Span 73 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz; 4 MHz Span 64 dBc

Double-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz; 1 MHz Span 74 dBc

CLK

= 50 MHz; f

OUT

= 5.00 MHz; 2 MHz Span 73 dBc

CLK

= 140 MHz; f

OUT

= 5.00 MHz; 4 MHz Span 60 dBc

Total Harmonic Distortion

CLK

= 50 MHz; f

OUT

= 1.00 MHz

= +25°C 66 dBc

MIN

to T

MAX

65 dBc

CLK

= 50 MHz; f

OUT

= 2.00 MHz 64 dBc

CLK

= 100 MHz; f

OUT

= 2.00 MHz 63 dBc

CLK

= 140 MHz; f

OUT

= 2.00 MHz 55 dBc

DAC PERFORMANCE

Glitch Impulse 10 pVs

DAC Crosstalk

23 dB

Data Feedthrough

4, 5

22 dB

Clock Feedthrough

4, 5

33 dB

NOTES

These max/min specifications are guaranteed by characterization over 4.75 V to 5.25 V range.

Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V

REF

DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.

Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.

TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured the 10% and 90% points. Timing reference points is 50% for inputs and outputs.

Specifications subject to change without notice.

= +5 V 6 5%

, V

REF

= 1.235 V, R

SET

= 560 V, C

= 10 pF. All specifications are for

= +258C unless otherwise noted, T

MAX

= 1108C)

–5–REV. A

ADV7123

3.3 V DYNAMIC SPECIFICATIONS

Parameter Min Typ Max Units

AC LINEARITY

Spurious-Free Dynamic Range to Nyquist

Single-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz 67 dBc

CLK

= 50 MHz; f

OUT

= 2.51 MHz 67 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz 63 dBc

CLK

= 50 MHz; f

OUT

= 20.2 MHz 55 dBc

CLK

= 100 MHz; f

OUT

= 2.51 MHz 62 dBc

CLK

= 100 MHz; f

OUT

= 5.04 MHz 60 dBc

CLK

= 100 MHz; f

OUT

= 20.2 MHz 54 dBc

CLK

= 100 MHz; f

OUT

= 40.4 MHz 48 dBc

CLK

= 140 MHz; f

OUT

= 2.51 MHz 57 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz 58 dBc

CLK

= 140 MHz; f

OUT

= 20.2 MHz 52 dBc

CLK

= 140 MHz; f

OUT

= 40.4 MHz 41 dBc

Double-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz 70 dBc

CLK

= 50 MHz; f

OUT

= 2.51 MHz 70 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz 65 dBc

CLK

= 50 MHz; f

OUT

= 20.2 MHz 54 dBc

CLK

= 100 MHz; f

OUT

= 2.51 MHz 67 dBc

CLK

= 100 MHz; f

OUT

= 5.04 MHz 63 dBc

CLK

= 100 MHz; f

OUT

= 20.2 MHz 58 dBc

CLK

= 100 MHz; f

OUT

= 40.4 MHz 52 dBc

CLK

= 140 MHz; f

OUT

= 2.51 MHz 62 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz 61 dBc

CLK

= 140 MHz; f

OUT

= 20.2 MHz 55 dBc

CLK

= 140 MHz; f

OUT

= 40.4 MHz 53 dBc

Spurious-Free Dynamic Range Within a Window

Single-Ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz; 1 MHz Span 77 dBc

CLK

= 50 MHz; f

OUT

= 5.04 MHz; 2 MHz Span 73 dBc

CLK

= 140 MHz; f

OUT

= 5.04 MHz; 4 MHz Span 64 dBc

Double-ended Output

CLK

= 50 MHz; f

OUT

= 1.00 MHz; 1 MHz Span 74 dBc

CLK

= 50 MHz; f

OUT

= 5.00 MHz; 2 MHz Span 73 dBc

CLK

= 140 MHz; f

OUT

= 5.00 MHz; 4 MHz Span 60 dBc

Total Harmonic Distortion

CLK

= 50 MHz; f

OUT

= 1.00 MHz

= +25°C 66 dBc

MIN

to T

MAX

65 dBc

CLK

= 50 MHz; f

OUT

= 2.00 MHz 64 dBc

CLK

= 100 MHz; f

OUT

= 2.00 MHz 64 dBc

CLK

= 140 MHz; f

OUT

= 2.00 MHz 55 dBc

DAC PERFORMANCE

Glitch Impulse 10 pVs

DAC Crosstalk

23 dB

Data Feedthrough

4, 5

22 dB

Clock Feedthrough

4, 5

33 dB

NOTES

These max/min specifications are guaranteed by characterization over 3.0 V to 3.6 V range.

Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, V

REF

DAC to DAC Crosstalk is measured by holding one DAC high while the other two are making low to high and high to low transitions.

Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.

TTL input values are 0 V to 3 V, with input rise/fall times ≤3 ns, measured the 10% and 90% points. Timing reference points is 50% for inputs and outputs.

Specifications subject to change without notice.

= +3.0 V–3.6 V

, V

REF

= 1.235 V, R

SET

= 680 V, C

= 10 pF. All specifications are

= +258C unless otherwise noted, T

MAX

= 1108C)

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