mpsk.rar_MPSK vhdl_mpsk

library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_MPSK is port ( clk:in std_logic; start:in std_logic; x:in std_logic; y:out std_logic ); end PL_MPSK; architecture behav of PL_MPSK is signal f1,f2,f3,f4 : std_logic; signal m: integer range 0 to 7; signal q: integer range 0 to 3; signal yyy:std_logic_vector(1 downto 0); signal yy:std_logic_vector(3 downto 0); begin process(clk) begin if rising_edge(clk) then if start ='0' then m<=0; -- elsif m=0 then m<=1; -- case yyy is -- when "00" => y<=f1 ; -- when "01" => y<=f2 ; --when "10" => y<=f3 ; --when "11" => y<=f4 ; -- when others => null; --end case; elsif m=7 then m<=0; case yyy is when "00" => yy<="0001"; when "01" => yy<="0010"; when "10" => yy<="0100"; when "11" => yy<="1000"; when others=> null; end case; --elsif m=7 then m<=0; else m<=m+1; end if; end if; end process; process(clk) begin if rising_edge(clk) then if start ='0' then q<=0; elsif q=1 then f2<='1';f4<='0';q<=q+1; elsif q=2 then f1<='0';f3<='1';q<=q+1; elsif q=3 then f2<='0';f4<='1';q<=0; else f1<='1';f3<='0';q<=q+1; --elsif q=3 then q<=0; -- else q<=q+1; end if; end if; end process; process(clk) begin if rising_edge(clk) then case m is when 2 => yyy(1)<=x; when 6 => yyy(0)<=x; when others => null; end case; end if; end process; --process(clk) -- begin --if rising_edge(clk) then -- if start='0' then q<=0; -- elsif q=1 then f2<='1';f4<='0'; -- elsif q=2 then f1<='0';f3<='1'; -- elsif q=3 then f2<='0';f4<='1'; -- else f1<='1';f3<='0'; -- end if; --end if; --end process; with yy select y<=f1 when "0001" , f2 when "0010" , f3 when "0100" , f4 when "1000" , '0' when others; end;