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-- Company:
-- Engineer:
--
-- Create Date: 12/20/2016 09:43:39 AM
-- Design Name:
-- Module Name: demtl16 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity demtl16 is
Port ( rst: in std_logic;
sel: in std_logic;
q: out std_logic_vector (15 downto 0);
cin : in STD_LOGIC;
reset: in std_logic
);
end demtl16;
architecture Behavioral of demtl16 is
signal temp: std_logic;
signal dem : integer range 0 to 49999999 :=0;
signal clk: std_logic;
begin
process (reset,cin) begin
if (reset ='1') then
temp <='0';
dem<=0;
elsif rising_edge (cin) then
if (dem=49999999) then
temp <= not (temp);
dem<=0;
else
dem<=dem+1;
end if;
end if;
end process;
clk<=temp;
process (clk,rst,sel)
variable x:integer range 0 to 15;
begin
if rst='1' then
x:=0;
else
if sel='1' then
if clk='1' and clk'event then
if x=15 then
x:=0;
else
x:=x+1;
end if;
end if;
else
if clk='1' and clk'event then
if x=0 then
x:=15;
else
x:=x-1;
end if;
end if;
end if;
end if;
case x is
when 0 => q<= "0000000000000001";
when 1 => q<= "0000000000000010";
when 2 => q<= "0000000000000100";
when 3 => q<= "0000000000001000";
when 4 => q<= "0000000000010000";
when 5 => q<= "0000000000100000";
when 6 => q<= "0000000001000000";
when 7 => q<= "0000000010000000";
when 8 => q<= "0000000100000000";
when 9 => q<= "0000001000000000";
when 10 => q<= "0000010000000000";
when 11 => q<= "0000100000000000";
when 12 => q<= "0001000000000000";
when 13 => q<= "0010000000000000";
when 14 => q<= "0100000000000000";
when 15 => q<= "1000000000000000";
end case;
end process;
end Behavioral;
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