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MachXO3ProgrammingandConfigurationUsageGuide.zip （1个子文件）

MachXO3ProgrammingandConfigurationUsageGuide.pdf 5.4MB

August 2017 Technical Note TN1279

www.latticesemi.com 1 TN1279_2.2

or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

Introduction

The MachXO3™ is an SRAM-based Programmable Logic Device that includes an internal Non-Volatile Configura-

tion Memory (NVCM) in the MachXO3L version and On-Chip Flash in the MachXO3LF version. This allows the

MachXO3L family to support the best of both worlds – infinitely configurable (SRAM) and non-volatile

(NVCM/Flash) capabilities. The MachXO3L/LF provides a rich set of features for programming and configuration of

the FPGA. You have many options available to you for building the programming solution that fits your needs. Each

of the options available will be described in detail so that you can put together the programming and configuration

solution that meets your needs.

MachXO3L/LF devices contain two types of memory, SRAM and NVCM (MachXO3L) or Flash (MachXO3LF).

SRAM memory contains the active configuration, essentially the “fuses” that define the behavior of the FPGA. The

active configuration is, in most cases, retrieved from a non-volatile memory. The non-volatile memory holds the

configuration data that is loaded into the FPGAs SRAM. The MachXO3L/LF provides an internal NVCM or Flash

memory that stores the configuration data loaded into the MachXO3L/LF SRAM.

MachXO3L/LF Features

Key programming and configuration features of MachXO3L devices are:

• Instant-on configuration from internal NVCM (MachXO3L) or Flash (MachXO3LF) – powers up in milliseconds

• Infinite number of configuration cycle through volatile SRAM technology

• MachXO3L multi-time (up to nine times) programmability through non-volatile technology (NVCM)

• Single-chip, secure solution

• Multiple programming and configuration interfaces:

— 1149.1 JTAG

— Self download

— Slave SPI

— Master SPI

— Dual Boot

— I

• Programming and configuration ports:

— Slave SPI

— Master SPI

— I

— JTAG

• (MachXO3LF) User Flash Memory (UFM) for non-volatile data storage:

— Configuration Flash memory overflow

— EBR Initialization data

— Application specific data

• (MachXO3LF) Transparent programming of non-volatile memory

• Optional dual boot with external SPI memory

• Optional security bits for design protection

• Optional Bitstream Compression support

• TransFR Capability

— Leave alone I/O using Non-JTAG implementation

• SED support

MachXO3 Programming and

Configuration Usage Guide

MachXO3 Programming and Configuration Usage Guide

Definition of Terms

This document uses the following terms to describe common functions:

•BIT – The BIT file is the configuration data for the MachXO3L/LF that is stored in an external SPI Flash. It is a

binary file and is programmed unmodified into the SPI Flash.

• Configuration: Configuration refers to a change in the state of the MachXO3L/LF SRAM memory cells.

• Configuration Data – This is the data read from the non-volatile memory and loaded into the FPGA’s SRAM

configuration memory. This is also referred to as a bitstream, or device bitstream.

• Configuration Mode: The configuration mode defines the method the MachXO3L/LF uses to acquire the config-

uration data from the non-volatile memory.

• Internal Flash Memory (MachXO3LF) – JED file or bit file can be programmed directly into the internal flash

sector. User does not need to know where an actual page of the configuration data starts. The MachXO3LF con-

figuration engine handles the parsing in the flash to SRAM transfer.

• Internal NVCM (MachXO3L) – JED file or bit file can be programmed directly into the internal non-volatile sector.

User does not need to know where an actual page of the configuration data starts. The MachXO3L configuration

engine handles the parsing in the NVCM to SRAM transfer.

•JEDEC – The JEDEC file contains the configuration data programmed into the MachXO3L/LF Configuration

NVCM or Flash. Format information is provided later in this technical note.

• Number Formats – The following nomenclature is used to denote the radix of numbers

— 0x: Numbers preceded by ‘0x’ are hexadecimal

— b (suffix): Numbers suffixed with ‘b’ are binary

— All other numbers are decimal

• Offline mode – Offline mode is a term that is applied to both non-volatile memory programming and SRAM con-

figuration. When using offline mode programming/configuration the FPGA no longer operates in user mode. The

contents of the non-volatile or SRAM configuration memory are updated, but the MachXO3L/LF does not per-

form your logic operations until offline mode programming/configuration is complete.

• Port – A port refers to the physical connection used to perform programming and some configuration operations.

Ports on the MachXO3L include JTAG, SPI, and I

C physical connections.

• Programming: Programming refers to the process used to alter the contents of the internal or external non-vola-

tile configuration memory.

• Transparent Mode (MachXO3LF) – Transparent mode is used to update the Configuration Flash, and User

Flash Memory while leaving the MachXO3LF in User Mode.

• User Mode – The MachXO3L is in user mode when configuration is complete, and the FPGA is performing the

logic functions you have programmed it to perform.

MachXO3 Programming and Configuration Usage Guide

Configuration Process and Flow

Prior to becoming operational, the FPGA goes through a sequence of states, including initialization, configuration

and wake-up.

Figure 1. Configuration Flow

The MachXO3L/LF sysCONFIG ports provide industry standard communication protocols for programming and

configuring the FPGA. Each of the protocols shown in Table 1 provides a way to access the MachXO3L/LF device’s

internal NVCM/Flash, or to load its configuration SRAM. The Memory Space Accessibility section provides infor-

mation about the capabilities of each sysCONFIG port.

The sysCONFIG ports capable of accessing the SRAM have a priority order. The operation of the Configuration

Logic is not defined when a low priority sysCONFIG port is interrupted by a higher priority sysCONFIG port. Do not

permit simultaneous access to the Configuration Logic using a sysCONFIG port.

Power not stable

PROGRAMN or

INITN=Low

User Mode

Configuration

Write SRAM Memory

ERROR

Power Up

VCC > 1.06V*

VCCIO > 1.06V*

INITN and DONE

Driven Low

Initialization

Wake Up

DONE Released

INITN Released

Device refresh

Device refresh:

• PROGRAMN falling edge

• IEEE 1532 REFRESH command

PROGRAMN de-asserted and t

INITL

expired

All configuration data received

* The voltage level is for the MachXO3 E device. Voltage level may vary for other devices.

MachXO3 Programming and Configuration Usage Guide

Power-up Sequence

In order for the MachXO3L/LF to operate, power must be applied to the device. During a short period of time, as the

voltages applied to the system rise, the FPGA will have an indeterminate state.

As power continues to ramp, a Power On Reset (POR) circuit inside the FPGA becomes active. The POR circuit,

once active, makes sure the external I/O pins are in a high-impedance state. It also monitors the V

and V

CCIO0

input rails. The POR circuit waits for the following conditions:

•V

> 1.06 V*

•V

CCIO0

> 1.06 V*

* The voltage level is for the MachXO3L/LF E device. Voltage level may vary for other devices.

When these conditions are met the POR circuit releases an internal reset strobe, allowing the device to begin its

initialization process. The MachXO3L/LF asserts INITN active low, and drives DONE low. When INITN and DONE

are asserted low the device moves to the initialization state, as shown in Figure 2.

Figure 2. Configuration from Power-On-Reset Timing

Initialization

The MachXO3L/LF enters the memory initialization phase immediately after the Power On Reset circuit drives the

INITN and DONE status pins low. The purpose of the initialization state is to clear all of the SRAM memory inside

the FPGA.

The FPGA remains in the initialization state until all of the following conditions are met:

•The t

INITL

time period has elapsed

• The PROGRAMN pin is deasserted

• The INITN pin is no longer asserted low by an external master

The INITN pin provides two functions during the initialization phase. The first is to indicate the FPGA is currently

clearing its configuration SRAM. The second is to act as an input preventing the transition from the initialization

state to the configuration state.

During the t

INITL

time period the FPGA is clearing the configuration SRAM. When the MachXO3L/LF is part of a

chain of devices each device will have different t

INITL

initialization times. The FPGA with the slowest t

INITL

parame-

ter can prevent other devices in the chain from starting to configure. Premature release of the INITN in a multi-

device chain may cause configuration of one or more chained devices to fail to configure intermittently.

Configuration

The rising edge of the INITN pin causes the FPGA to enter the configuration state. The FPGA is able to accept the

configuration bitstream created by the Diamond development tools.

The MachXO3L/LF begins fetching configuration data from non-volatile memory. The memory used to configure

the MachXO3L/LF is either the internal memory, or an external SPI Flash. The MachXO3L/LF does not leave the

Configuration state if there are no memories with valid configuration data. It is necessary to program the non-vola-

tile memory internal or attached to the FPGA, or to program it using the JTAG port.

DONE

INITN

CCIO

INITL

MachXO3 Programming and Configuration Usage Guide

During the time the FPGA receives its configuration data the INITN control pin takes on its final function. INITN is

used to indicate an error exists in the configuration data. When INITN is high, configuration proceeds without issue.

If INITN is asserted low, an error has occurred and the FPGA will not operate.

Wake-up

Wake-up is the transition from configuration mode to user mode. The MachXO3L/LF’s fixed four-phase wake-up

sequence starts when the device has correctly received all of its configuration data. When all configuration data is

received, the FPGA asserts an internal DONE status bit. The assertion of the internal DONE causes a Wake Up

state machine to run that sequences four controls. The four control strobes are:

• External DONE

• Global Write Disable (GWDISn)

• Global Output Enable (GOE)

• Global Set/Reset (GSR)

The first phase of the Wake-Up process is for the MachXO3L/LF to release the Global Output Enable. When it is

asserted, permits the FPGA’s I/O to exit a high-impedance state and take on their programmed output function.

The FPGA inputs are always active. The input signals are prevented from performing any action on the FPGA flip-

flops by the assertion of the Global Set/Reset (GSR).

The second phase of the Wake-Up process releases the Global Set/Reset and the Global Write Disable controls.

The Global Set/Reset is an internal strobe that, when asserted, causes all I/O flip-flops, Look Up Table (LUT) flip-

flops, distributed RAM output flip-flops, and Embedded Block RAM output flip-flops that have the GSR enabled

attribute to be set/cleared per their hardware description language definition.

The Global Write Disable is a control that overrides the write enable strobe for all RAM logic inside the FPGA. The

inputs on the FPGA are always active, as mentioned in the Global Output Enable section. Keeping GWDIS

asserted prevents accidental corruption of the instantiated RAM resources inside the FPGA.

The last phase of the Wake-Up process is to assert the external DONE pin. The external DONE is a bi-directional,

open-drain I/O only when it is enabled. An external agent that holds the external DONE pin low prevents the wake-

up process of the MachXO3L/LF from proceeding. Only after the external DONE, if enabled, is active high does the

final wake-up phase complete. Wake-Up completes uninterrupted when the external DONE pin is not enabled.

Once the final wake-up phase is complete, the FPGA enters user mode.

User Mode

The MachXO3L/LF enters User Mode immediately following the Wake-Up sequence has completed. User Mode is

the point in time when the MachXO3L/LF begins performing the logic operations you designed. The MachXO3L/LF

remains in this state until one of three events occurs:

• The PROGRAMN input pin is asserted

• A REFRESH command is received via one of the configuration ports

• Power is cycled

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