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《ADuC7060开发指南》在嵌入式系统设计中，微控制器（MCU）扮演着至关重要的角色，而Analog Devices公司的ADuC7060是一款集成了高性能数字信号处理与模拟功能的混合信号微控制器，广泛应用于各种工业、医疗以及消费类电子产品。这份“ADuC7060.rar”压缩包提供的文档，正是针对ADuC7060的开发指导，旨在帮助开发者充分利用其强大功能，快速高效地完成项目开发。 ADuC7060的核心是一个增强型8051内核，具有高速运算能力和丰富的片上资源。它包含一个25MHz的内部振荡器，可实现快速启动和低功耗运行。此外，该芯片还集成了一颗12位ADC，采样速率高达200ksps，确保了高精度的数据采集。内置的DA转换器和精密的模拟电路，使其在处理模拟信号时表现出色。在I/O接口方面，ADuC7060提供了丰富的端口，支持GPIO、UART、SPI、I2C等多种通信协议，可以轻松连接外围设备。此外，它还包含了多种定时器和PWM模块，适用于电机控制、脉宽调制等应用。这些特性使得ADuC7060在设计中具有高度的灵活性和适应性。在软件开发方面，ADuC7060支持标准的8051汇编语言和C编译器，开发者可以利用Analog Devices提供的IDE或者第三方工具进行编程。压缩包中的"aduc7060.pdf"文档会详细介绍如何配置和编程这些功能，包括初始化设置、中断处理、外设操作等，为开发者提供详尽的指导。开发ADuC7060时，需要注意以下关键点： 1. **电源管理**：ADuC7060具有多级电源管理功能，可以根据应用需求调整工作模式，实现低功耗运行。 2. **模拟电路设计**：由于内置ADC和DAC，需要合理规划模拟信号路径，避免噪声干扰，确保测量精度。 3. **时钟系统**：正确配置内部振荡器或外部时钟源，以满足系统性能要求。 4. **编程模型**：理解8051指令集和中断结构，是编写高效代码的关键。 5. **外设接口**：根据应用选择合适的通信协议，正确配置I/O口，连接外围设备。 6. **调试技巧**：利用仿真器或JTAG接口进行程序调试，找出并修复问题。通过深入学习“aduc7060.pdf”，开发者不仅可以掌握ADuC7060的基本操作，还能了解如何优化系统性能，提高产品可靠性。这份文档是ADuC7060开发者的必备参考资料，对于任何计划使用ADuC7060的项目都是宝贵的财富。

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Low Power, Precision Analog Microcontroller

Dual

Sigma-Delta ADCs,

Flash/EE, ARM7TDMI

ADuC7060/ADuC7061

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

Analog input/output

Dual (24-bit) ADCs

Single-ended and differential inputs

Programmable ADC output rate (4 Hz to 8 kHz)

Programmable digital filters

Built-in system calibration

Low power operation mode

Primary (24-bit) ADC channel

2 differential pairs or 4 single-ended channels

PGA (1 to 512) input stage

Selectable input range: ±2.34 mV to ±1.2 V

30 nV rms noise

Auxiliary (24-bit) ADC: 4 differential pairs or 7 single-

ended channels

On-chip precision reference (±10 ppm/°C)

Programmable sensor excitation current sources

200 μA to 2 mA current source range

Single 14-bit voltage output DAC

Microcontroller

ARM7TDMI core, 16-/32-bit RISC architecture

JTAG port supports code download and debug

Multiple clocking options

Memory

32 kB (16 kB × 16) Flash/EE memory, including 2 kB kernel

4 kB (1 kB × 32) SRAM

Tools

In-circuit download, JTAG based debug

Low cost, QuickStart™ development system

Communications interfaces

SPI interface (5 Mbps)

4-byte receive and transmit FIFOs

UART serial I/O and I

C (master/slave)

On-chip peripherals

4× general-purpose (capture) timers including

Wake-up timer

Watchdog timer

Vectored interrupt controller for FIQ and IRQ

8 priority levels for each interrupt type

Interrupt on edge or level external pin inputs

16-bit, 6-channel PWM

General-purpose inputs/outputs

Up to 14 GPIO pins that are fully 3.3 V compliant

Power

AVDD/DVDD specified for 2.5 V (±5%)

Active mode: 2.74 mA (@ 640 kHz, ADC0 active)

10 mA (@ 10.24 MHz, both ADCs active)

Packages and temperature range

Fully specified for −40°C to +125°C operation

32-lead LFCSP (5 mm × 5 mm)

48-lead LFCSP and LQFP

Derivatives

32-lead LFCSP (ADuC7061)

48-lead LQFP and 48-lead LFCSP (ADuC7060)

APPLICATIONS

Industrial automation and process control

Intelligent, precision sensing systems, 4 mA to 20 mA

loop-based smart sensors

GENERAL DESCRIPTION

The ADuC706x series are fully integrated, 8 kSPS, 24-bit data acqui-

sition systems incorporating high performance multichannel

sigma-delta (Σ-Δ) analog-to-digital converters (ADCs), 16-bit/

32-bit ARM7TDMI® MCU, and Flash/EE memory on a single chip.

The ADCs consist of a primary ADC with two differential pairs or

four single-ended channels and an auxiliary ADC with up to seven

channels. The ADCs operate in single-ended or differential input

mode. A single-channel buffered voltage output DAC is available

on chip. The DAC output range is programmable to one of four

voltage ranges.

The devices operate from an on-chip oscillator and a PLL gene-

rating an internal high frequency clock up to 10.24 MHz. The

microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC

machine offering up to 10 MIPS peak performance; 4 kB of SRAM

and 32 kB of nonvolatile Flash/EE memory are provided on chip.

The ARM7TDMI core views all memory and registers as a single

linear array.

The ADuC706x contains four timers. Timer1 is a wake-up timer

with the ability to bring the part out of power saving mode. Timer2

is configurable as a watchdog timer. A 16-bit PWM with six output

channels is also provided. The ADuC706x contains an advanced

interrupt controller. The vectored interrupt controller (VIC) allows

every interrupt to be assigned a priority level. It also supports

nested interrupts to a maximum level of eight per IRQ and FIQ.

When IRQ and FIQ interrupt sources are combined, a total of 16

nested interrupt levels is supported. On-chip factory firmware

supports in-circuit serial download via the UART serial interface

ports and nonintrusive emulation via the JTAG interface. The parts

operate from 2.375 V to 2.625 V over an industrial temperature

range of −40°C to +125°C.

ADuC7060/ADuC7061

Rev. B | Page 2 of 108

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications ..................................................................................... 5

Electrical Specifications ............................................................... 5

Timing Specifications ................................................................ 10

Absolute Maximum Ratings .......................................................... 14

ESD Caution ................................................................................ 14

Pin Configurations and Function Descriptions ......................... 15

Terminology .................................................................................... 20

Overview of the ARM7TDMI Core ............................................. 21

Thumb Mode (T) ........................................................................ 21

Multiplier (M) ............................................................................. 21

EmbeddedICE (I) ....................................................................... 21

ARM Registers ............................................................................ 21

Interrupt Latency ........................................................................ 22

Memory Organization ............................................................... 22

Flash/EE Control Interface ........................................................ 23

Memory Mapped Registers ....................................................... 26

Complete MMR Listing ............................................................. 27

Reset ............................................................................................. 32

Oscillator, PLL, and Power Control ............................................. 33

Clocking System ......................................................................... 33

Power Control System ................................................................ 33

ADC Circuit Information .............................................................. 37

Reference Sources ....................................................................... 38

Diagnostic Current Sources ...................................................... 38

Sinc3 Filter ................................................................................... 39

ADC Chopping ........................................................................... 39

Programmable Gain Amplifier ................................................. 39

Excitation Sources ...................................................................... 39

ADC Low Power Mode .............................................................. 39

ADC Comparator and Accumulator ....................................... 40

Temperature Sensor ................................................................... 40

ADC MMR Interface ................................................................. 40

Example Application Circuits ................................................... 53

DAC Peripherals ............................................................................. 55

DAC .............................................................................................. 55

MMR Interface ........................................................................... 55

Using the DAC ............................................................................ 56

Nonvolatile Flash/EE Memory ..................................................... 57

Flash/EE Memory Reliability .................................................... 57

Programming .............................................................................. 57

Processor Reference Peripherals ................................................... 58

Interrupt System ......................................................................... 58

IRQ ............................................................................................... 58

Fast Interrupt Request (FIQ) .................................................... 59

Programmed Interrupts............................................................. 60

Vectored Interrupt Controller (VIC) ....................................... 60

VIC MMRs .................................................................................. 60

Timers .............................................................................................. 65

Timer0.......................................................................................... 66

Timer1 or Wake-Up Timer ....................................................... 68

Timer2 or Watchdog Timer ...................................................... 70

Timer3.......................................................................................... 72

Pulse-Width Modulator ................................................................. 74

Pulse-Width Modulator General Overview ........................... 74

UART Serial Interface .................................................................... 79

Baud Rate Generation ................................................................ 79

UART Register Definitions ....................................................... 79

C ..................................................................................................... 85

Configuring External Pins for I

C Functionality ................... 85

Serial Clock Generation ............................................................ 86

C Bus Addresses ....................................................................... 86

C Registers ................................................................................ 86

Serial Peripheral Interface ............................................................. 95

MISO (Master In, Slave Out) Pin ............................................. 95

MOSI (Master Out, Slave In) Pin ............................................. 95

SCLK (Serial Clock I/O) Pin ..................................................... 95

Slave Select (P0.0/

) Input Pin ............................................... 95

Configuring External Pins for SPI Functionality ................... 95

SPI Registers ................................................................................ 96

General-Purpose I/O ................................................................... 100

GPxCON Registers................................................................... 100

GPxDAT Registers ................................................................... 101

GPxSET Registers ..................................................................... 101

GPxCLR Registers .................................................................... 101

GPxPAR Registers .................................................................... 101

ADuC7060/ADuC7061

Rev. B | Page 3 of 108

Hardware Design Considerations .............................................. 103

Power Supplies .......................................................................... 103

Outline Dimensions ...................................................................... 104

Ordering Guide ......................................................................... 105

REVISION HISTORY

2/10—Rev. A to Rev. B

Changes to Features Section ............................................................ 1

Changes to Table 1 ............................................................................ 4

Changes to Digital I/O Voltage to DGND Parameter ................ 14

Changes to Pin 19, Pin 20, and Pin 45 Descriptions (Table 8) .. 16

Changes to Pin 13, Pin 14, and Pin 29 Descriptions (Table 9) .. 18

Changes to Bit 8 in Table 14 ........................................................... 23

Changes to Table 20 ........................................................................ 28

Changes to Power Control System Section .................................. 34

Added Table 32 ................................................................................ 35

Changes to Endnote 2 and Endnote 3 of Table 34 ...................... 36

Changes to Table 42 ........................................................................ 42

Changes to Bit 12 and Bits[3:0] in Table 43 ................................. 44

Changes to Bit 12 in Table 44 ........................................................ 45

Changes to Endnote 2 in Table 45 ................................................. 47

Changes to Bit 5 in Table 63 ........................................................... 55

Changes to Serial Downloading (In-Circuit Programming)

Section .............................................................................................. 57

Changes to Priority Registers Section .......................................... 61

Changes to GPxPAR Registers Section ......................................101

6/09—Rev. 0 to Rev. A

Added ADuC7061 .............................................................. Universal

Added New Package CP-32-4 ........................................... Universal

Changes to Features Section ............................................................ 1

Changes to General Description Section ....................................... 1

Changes to Figure 1 ........................................................................... 4

Changes to Table 1 ............................................................................ 7

Deleted Endnote to Table 2 ............................................................ 10

Changes to Endnotes, Table 3 and Table 4 ................................... 11

Changes to Endnotes, Table 5 ........................................................ 12

Changes to Endnotes, Table 6 ........................................................ 13

Changes to Figure 7 and Table 8 ................................................... 15

Added Figure 8 and Table 9, Renumbered Sequentially ............ 18

Changes to Flash EE/Control Interface Section .......................... 23

Change to Code 0x04 Description, Table 15 ............................... 24

Change to Bit 31 Description, Table 16 ........................................ 25

Changes to Table 17 ........................................................................ 27

Changes to Table 19 T0CLRI and Table 20 .................................. 28

Changes to Endnote, Table 21 ....................................................... 29

Change to SPITX Default Value, Table 25 ................................... 30

Changes to External Clock Selection Section ............................. 33

Changes to ADC Circuit Information Section ............................ 36

Change to Column Heading Table 35 .......................................... 37

Change to Bit 6 Description, Table 39 .......................................... 40

Change to Bit 12 Description, Table 43 ........................................ 44

Changes to Primary Channel ADC Data Register Section

and Auxiliary Channel ADC Data Register Section .................. 48

Change to Table 59 and Figure 17 ................................................. 51

Changes to Using the DAC Section .............................................. 55

Changes to Nonvolatile Flash/EE Memory Section and

Programming Section ..................................................................... 56

Changes to Vectored Interrupt Controller (VIC) Section ......... 59

Changes to Priority Registers Section .......................................... 60

Change to Table 73 .......................................................................... 61

Changes to Figure 23 ...................................................................... 65

Changes Table 78 ............................................................................. 66

Changes to Figure 24 and Table 79 ............................................... 68

Changes to Timer2 Interface Section and Figure 25 .................. 69

Changes to Timer3 Capture Register Section ............................. 71

Change to Bits[16:12] Description, Table 81 ............................... 72

Changes Pulse-Width Modulator General Overview Section,

Table 82, and Figure 26 ................................................................... 73

Changes to Table 84 Column Headings ....................................... 75

Changes to Table 92 ........................................................................ 82

Changes to Bit 1, Table 102 ............................................................ 90

Changes to Bit 11 Description, Table 105 .................................... 95

Changes to SPIMDE Bit Description, Table 106 ......................... 97

Updated Outline Dimensions ...................................................... 103

Changes to Ordering Guide ......................................................... 104

4/09—Revision 0: Initial Version

ADuC7060/ADuC7061

Rev. B | Page 4 of 108

PRECISION ANALOG PERIPHERALS

FUNCTIONAL BLOCK DIAGRAM

POR

MEMORY

32kB FLASH

4kB RAM

ARM7TDMI

MCU

10MHz

ON-CHIP

OSC (3%)

PLL

4× TIMERS

WDT

W/U TIMER

PWM

GPIO PORT

UART PORT

SPI PORT

C PORT

VIC

(VECTORED

INTERRUPT

CONTROLLER)

MUX

24-BIT

Σ-Δ

ADC

BUF

24-BIT

Σ-Δ ADC

PGA

PRECISION

REFERENCE

TEMP

SENSOR

14-BIT

DAC

RESET

XTALO

XTALI

ADC0

ADC1

ADC5

ADC4

ADC3

ADC2

ADC6

ADC7

ADC8

ADC9

IEXC0

IEXC1

DAC0

VREF+

VREF–

GND_SW

ADuC7060/

ADuC7061

BUF

07079-001

Figure 1.

ADuC7060/ADuC7061

Rev. B | Page 5 of 108

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

= 2.5 V ± 5%, VREF+ = 1.2 V, VREF− = GND, f

CORE

= 10.24 MHz driven from an external 32.768 kHz watch crystal or on-chip

oscillator, all specifications T

= −40°C to +125°C, unless otherwise noted. Output noise specifications can be found in Table 36 (primary

ADC) and Table 38 (ADC auxiliary channel).

Table 1. ADuC706x Specifications

Parameter Test Conditions/Comments Min Typ Max Unit

ADC SPECIFICATIONS

For all ADC specifications,

assume normal operating mode

unless specifically stated

otherwise

Conversion Rate

Chop off, ADC normal operating

mode

50 8000 Hz

Chop on, ADC normal operating

mode

4 2600 Hz

Chop on, ADC low power mode 1 650 Hz

Main Channel

No Missing Codes

Chop off (f

ADC

≤ 1 kHz) 24 Bits

Chop on (f

ADC

≤ 666 Hz) 24 Bits

Integral Nonlinearity

1, 2

Gain = 4 ±15 ppm of FSR

Offset Error

3, 4

Chop off, offset error is in the

order of the noise for the pro-

grammed gain and update rate

following calibration

−27 ±8 +27 V

Offset Error

1, 3, 4

Chop on −2.7 ±0.5 +2.7 V

Offset Error Drift vs.

Temperature

Chop off (with gain ≤ 64) 650/PGA_GAIN nV/°C

Chop on (with gain ≤ 64) 10 nV/°C

Full-Scale Error

1, 6 , 7, 8

Normal mode −1 ±0.5 +1 mV

Full-Scale Error

6, 8

Low power mode −2 ±1.0 +2 mV

Gain Drift vs. Temperature

5 ppm/°C

PGA Gain Mismatch Error ±0.1 %

Power Supply Rejection

Chop on, ADC = 1 V (gain = 1) 65 dB

Chop on, ADC = 7.8 mV (gain =

128)

84.7 113 dB

Chop off, ADC = 1 V (gain = 1) 56 65 dB

Auxiliary Channel

No Missing Codes

Chop off (f

ADC

≤ 1 kHz) 24 Bits

Chop on (f

ADC

≤ 666 Hz) 24 Bits

Integral Nonlinearity

±15 ppm of FSR

Offset Error

Chop off −120 ±30 +100 V

Offset Error

1, 4

Chop on −1.5 ±0.5 +3.2 V

Offset Error Drift vs.

Temperature

Chop off 200 nV/°C

Chop on 10 nV/°C

Full-Scale Error

1, 6, 7, 8

Normal mode −1 ±0.5 +1 mV

Full-Scale Error

1, 6, 8

Low power mode −2 ±1.0 +2 mV

Gain Drift vs. Temperature

3 ppm/°C

Power Supply Rejection

Chop on, ADC = 1 V 55 65 dB

Chop off, ADC = 1 V 53 65 dB

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