wb_handler-1.0.1.tar.gz_fgpa_wishbone

Copyright (c) 2005-2006 Salvador E. Tropea <salvador en inti gov ar> Copyright (c) 2005-2006 Instituto Nacional de Tecnolog�a Industrial This core is a helper used to write testbenches for cores connected to Wishbone. The core replaces the Wishbone master using a component that's controlled by the testbench. Usage examples can be found in the testbenches of I2C and SIC packages. If you use ghdl and you want to create a library just run make. Instantiation example: -- Testbench side signal addr : std_logic_vector(8-1 downto 0); signal datai : std_logic_vector(8-1 downto 0); signal datao : std_logic_vector(8-1 downto 0); signal rd : std_logic:='0'; signal wr : std_logic:='0'; signal rde : std_logic; signal wre : std_logic; -- Wishbone side signal wb_rst : std_logic:='1'; signal wb_clk : std_logic;--:='0'; signal wb_adr : std_logic_vector(8-1 downto 0); signal wb_dati : std_logic_vector(8-1 downto 0):=(others => 'Z'); signal wb_dato : std_logic_vector(8-1 downto 0); signal wb_we : std_logic; signal wb_stb : std_logic; signal wb_cyc : std_logic; signal wb_ack : std_logic:='0'; -- Wishbone master simulator wb_master: WBHandler port map( addr_i => addr, data_i => datai, data_o => datao, rd_i => rd, wr_i => wr, rde_o => rde, wre_o => wre, wb_rst_i => wb_rst, wb_clk_i => wb_clk, wb_ack_i => wb_ack, wb_adr_o => wb_adr, wb_dat_i => wb_dati, wb_dat_o => wb_dato, wb_we_o => wb_we, wb_stb_o => wb_stb, wb_cyc_o => wb_cyc); Simulating a read: WBRead(addr,SIC_FLGR,rd,rde); assert datao="00000000" and irq='0' report "Pending interrupts?!" severity failure; In this example datao is the result of reading SIC_FLGR address. Simulating a write: WBWrite(addr,SIC_ENAR,datai,"00000001",wr,wre); In this example we are writing "00000001" to the SIC_ENAR address.