vnu.rar_UNIT_THE_vnu资源-CSDN文库

共38个文件

vhd：6个

wdb：5个

prj：4个

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unit

12 浏览量 2022-09-19 21:40:10 上传评论收藏 663KB RAR 举报

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收起资源包目录

vnu.rar （38个子文件）

vnu

xst

projnav.tmp

work

work.vdbl 6KB

work.vdbx 65B

vnu_xst.xrpt 8KB

vnu.prj 21B

vnu.gise 4KB

vnu.vhd.bak 2KB

vnu.lso 6B

isim.log 488B

iseconfig

vnu.xreport 19KB

vnu.projectmgr 7KB

vnu_isim_beh.exe 117KB

vnu_envsettings.html 9KB

fuse.log 1KB

vnu_beh.prj 21B

templates

_xmsgs

xst.xmsgs 586B

pn_parser.xmsgs 2KB

vnu_summary.html 4KB

vnu4.vhd 2KB

vnu4_isim_beh.wdb 11KB

vnu2_isim_beh.wdb 11KB

vnu3.vhd 2KB

vnu.xst 1KB

ipcore_dir

vnu.xise 36KB

vnu2.vhd 2KB

vnu.cmd_log 108B

vnu_ise12migration.zip 588KB

divi.vhd 2KB

divi_stx_beh.prj 27B

divi_isim_beh.wdb 8KB

vnu_isim_beh.wdb 13KB

vnu1_isim_beh.wdb 11KB

xilinxsim.ini 16B

vnu.syr 4KB

vnu1.vhd 2KB

webtalk_pn.xml 3KB

vnu.vhd 2KB

isim.cmd 44B

vnu_stx_beh.prj 26B

<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <center><big><big>System Settings</big></big></center> <A NAME="Environment Settings"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='5'> Environment Settings </TD> </tr> <tr bgcolor='#ffff99'> <td>Environment Variable</td> <td>xst</td> <td>ngdbuild</td> <td>map</td> <td>par</td> </tr> <tr> <td>PATHEXT</td> <td>.COM; .EXE; .BAT; .CMD; .VBS; .VBE; .JS; .JSE; .WSF; .WSH; .MSC</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>Path</td> <td>C:\Xilinx\13.2\ISE_DS\ISE\\lib\nt; C:\Xilinx\13.2\ISE_DS\ISE\\bin\nt; C:\Xilinx\13.2\ISE_DS\PlanAhead\bin; C:\Xilinx\13.2\ISE_DS\ISE\bin\nt; C:\Xilinx\13.2\ISE_DS\ISE\lib\nt; C:\Xilinx\13.2\ISE_DS\EDK\bin\nt; C:\Xilinx\13.2\ISE_DS\EDK\lib\nt; C:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt\bin; C:\Xilinx\13.2\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin; C:\Xilinx\13.2\ISE_DS\EDK\gnuwin\bin; C:\Xilinx\13.2\ISE_DS\common\bin\nt; C:\Xilinx\13.2\ISE_DS\common\lib\nt; C:\Windows\system32; C:\Windows; C:\Windows\System32\Wbem; C:\Windows\System32\WindowsPowerShell\v1.0\; c:\Xilinx\bin\nt; C:\Program Files\HI-TECH Software\PICC-Lite\9.50\bin; E:\PROGRA~1\PICC; C:\PROGRA~1\PICC; E:\bin; E:\bin\win32; E:\Install matlab\runtime\win32; E:\Install matlab\bin; C:\altera\90\modelsim_ase\win32aloem</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX</td> <td>C:\Xilinx\13.2\ISE_DS\ISE\</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_DSP</td> <td>C:\Xilinx\13.2\ISE_DS\ISE</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_EDK</td> <td>C:\Xilinx\13.2\ISE_DS\EDK</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> <tr> <td>XILINX_PLANAHEAD</td> <td>C:\Xilinx\13.2\ISE_DS\PlanAhead</td> <td>< data not available ></td> <td>< data not available ></td> <td>< data not available ></td> </tr> </TABLE> <A NAME="Synthesis Property Settings"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='4'>Synthesis Property Settings </TD> </tr> <tr bgcolor='#ffff99'> <td>Switch Name</td> <td>Property Name</td> <td>Value</td> <td>Default Value</td> </tr> <tr> <td>-ifn</td> <td> </td> <td>vnu.prj</td> <td> </td> </tr> <tr> <td>-ifmt</td> <td> </td> <td>mixed</td> <td>Mixed</td> </tr> <tr> <td>-ofn</td> <td> </td> <td>vnu</td> <td> </td> </tr> <tr> <td>-ofmt</td> <td> </td> <td>NGC</td> <td>NGC</td> </tr> <tr> <td>-p</td> <td> </td> <td>xc6vlx75t-3-ff484</td> <td> </td> </tr> <tr> <td>-top</td> <td> </td> <td>vnu</td> <td> </td> </tr> <tr> <td>-opt_mode</td> <td>Optimization Goal</td> <td>Speed</td> <td>Speed</td> </tr> <tr> <td>-opt_level</td> <td>Optimization Effort</td> <td>1</td> <td>1</td> </tr> <tr> <td>-power</td> <td>Power Reduction</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-iuc</td> <td>Use synthesis Constraints File</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-keep_hierarchy</td> <td>Keep Hierarchy</td> <td>No</td> <td>No</td> </tr> <tr> <td>-netlist_hierarchy</td> <td>Netlist Hierarchy</td> <td>As_Optimized</td> <td>As_Optimized</td> </tr> <tr> <td>-rtlview</td> <td>Generate RTL Schematic</td> <td>Yes</td> <td>No</td> </tr> <tr> <td>-glob_opt</td> <td>Global Optimization Goal</td> <td>AllClockNets</td> <td>AllClockNets</td> </tr> <tr> <td>-read_cores</td> <td>Read Cores</td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-write_timing_constraints</td> <td>Write Timing Constraints</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-cross_clock_analysis</td> <td>Cross Clock Analysis</td> <td>NO</td> <td>No</td> </tr> <tr> <td>-bus_delimiter</td> <td>Bus Delimiter</td> <td><></td> <td><></td> </tr> <tr> <td>-slice_utilization_ratio</td> <td>Slice Utilization Ratio</td> <td>100</td> <td>100</td> </tr> <tr> <td>-bram_utilization_ratio</td> <td>BRAM Utilization Ratio</td> <td>100</td> <td>100</td> </tr> <tr> <td>-dsp_utilization_ratio</td> <td>DSP Utilization Ratio</td> <td>100</td> <td>100</td> </tr> <tr> <td>-reduce_control_sets</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-fsm_extract</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-fsm_encoding</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-safe_implementation</td> <td> </td> <td>No</td> <td>No</td> </tr> <tr> <td>-fsm_style</td> <td> </td> <td>LUT</td> <td>LUT</td> </tr> <tr> <td>-ram_extract</td> <td> </td> <td>Yes</td> <td>Yes</td> </tr> <tr> <td>-ram_style</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-rom_extract</td> <td> </td> <td>Yes</td> <td>Yes</td> </tr> <tr> <td>-shreg_extract</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-rom_style</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-auto_bram_packing</td> <td> </td> <td>NO</td> <td>No</td> </tr> <tr> <td>-resource_sharing</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-async_to_sync</td> <td> </td> <td>NO</td> <td>No</td> </tr> <tr> <td>-use_dsp48</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-iobuf</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-max_fanout</td> <td> </td> <td>100000</td> <td>100000</td> </tr> <tr> <td>-bufg</td> <td> </td> <td>32</td> <td>32</td> </tr> <tr> <td>-register_duplication</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-register_balancing</td> <td> </td> <td>No</td> <td>No</td> </tr> <tr> <td>-optimize_primitives</td> <td> </td> <td>NO</td> <td>No</td> </tr> <tr> <td>-use_clock_enable</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-use_sync_set</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-use_sync_reset</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-iob</td> <td> </td> <td>Auto</td> <td>Auto</td> </tr> <tr> <td>-equivalent_register_removal</td> <td> </td> <td>YES</td> <td>Yes</td> </tr> <tr> <td>-slice_utilization_ratio_maxmargin</td> <td> </td> <td>5</td> <td>0</td> </tr> </TABLE> <A NAME="Operating System Information"></A>   <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TD ALIGN=CENTER COLSPAN='5'> Operating System Information </TD> </tr> <tr bgcolor='#ffff99'> <td>Operating System Information</td> <td>xst</td> <td>ngdbuild</td> <td>map</td> <td>par</td> </tr> <tr> <td>CPU Architecture/Speed</td> <td>Intel(R) Core(TM)2 Duo CPU T6600 @ 2.20GHz/2194 MHz</td> <td><  data not available  ></td> <td><

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