#include <linux/kernel.h>
#include <linux/version.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/fcntl.h>
#include <linux/mm.h>
#include <linux/miscdevice.h>
#include <linux/proc_fs.h>
#include <linux/fs.h>
#include <linux/slab.h>
//#include <linux/smp_lock.h>
#include <linux/init.h>
#include <asm/uaccess.h>
//#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/system.h>
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/string.h>
#include <linux/list.h>
//#include <asm/semaphore.h>
//#include <asm/delay.h>
#include <linux/timer.h>
#include <linux/delay.h>
#include <linux/moduleparam.h>
#include "gpio_i2c.h"
#include "adv7441.h"
#include "adv7441_def.h"
//#define printk printf
#define DEBUG_ADV7400 1
//static unsigned int ADV7400_dev_open_cnt =0;
#ifndef VXWORKS
#define gpio_i2c0_read gpio_i2c_read
#define gpio_i2c0_write gpio_i2c_write
#endif
#define CLAER_I2C_ERROR(i2c_addr)
//gpio_i2c_read(i2c_addr,0xb1) //2014-5-9 for correct i2c error
/*GPIO4_6, DVI_1_DET,
GPIO4_7, DVI_1_HPD*/
#define GPIO_4_BASE 0x20190000
#define GPIO_4_DIR IO_ADDRESS(GPIO_4_BASE + 0x400)
#define GPIO_4_6_DATA IO_ADDRESS(GPIO_4_BASE + 0x100)
#define GPIO_4_7_DATA IO_ADDRESS(GPIO_4_BASE + 0x200)
/*GPIO12_5, DVI_2_DET,
GPIO12_4, DVI_2_HPD*/
#define GPIO_12_BASE 0x20210000
#define GPIO_12_DIR IO_ADDRESS(GPIO_12_BASE + 0x400)
#define GPIO_12_4_DATA IO_ADDRESS(GPIO_12_BASE + 0x40)
#define GPIO_12_5_DATA IO_ADDRESS(GPIO_12_BASE + 0x80)
#define GPIO_HW_REG(reg) *((volatile unsigned int *)(reg))
VIDIN_FMT_E gAdv_Fmt[2]= {VIDIN_FMT_MAX, VIDIN_FMT_MAX};
ADV7441_SRC_TYPE_E gAdvSrcType[2] ={VGA_IN, VGA_IN};
unsigned char adv7400_cvbs_mode[]=
{
CVBS_FMT_NTSC_M, //NTSC_M
CVBS_FMT_NTSC_443, //NTSC_443
CVBS_FMT_PAL_M, //PAL_M
CVBS_FMT_PAL_60, //PAL_60
CVBS_FMT_PAL_BGHID, //PAL_BG
CVBS_FMT_SECAM, //SECAM
CVBS_FMT_PAL_N, //PAL_N
CVBS_FMT_SECAM_525 //SECAM_525
};
MODEDETECTTB adv7441_Ypbpr_mode[]=
{
{YPBPR_FMT_720_480_I60, LCF_480I, FCL_480I },
{YPBPR_FMT_720_576_I50, LCF_576I, FCL_576I},
{YPBPR_FMT_720_480_P60, LCF_480P, FCL_480P},
{YPBPR_FMT_720_576_P50, LCF_576P, FCL_576P},
{YPBPR_FMT_1280_720P60, LCF_720P60, FCL_720P60},
{YPBPR_FMT_1280_720P50, LCF_720P50, FCL_720P50},
{YPBPR_FMT_1920_1080_I60, LCF_1080I60, FCL_1080I60},
{YPBPR_FMT_1920_1080_I50, LCF_1080I50, FCL_1080I50},
{YPBPR_FMT_1920_1080_P60, LCF_1080P60, FCL_1080P60},
{YPBPR_FMT_1920_1080_P50, LCF_1080P50, FCL_1080P50},
{YPBPR_FMT_1920_1080_P30, LCF_1080P30, FCL_1080P30},
{YPBPR_FMT_1920_1080_P25, LCF_1080P25, FCL_1080P25},
{YPBPR_FMT_1920_1080_P24, LCF_1080P24, FCL_1080P24},
{0xff, 0xffff, 0xffff},
};
MODEDETECTTB adv7441_VGA_mode[]=
{
{VGA_FMT_640x480_60, 525, 1868},
{VGA_FMT_640x480_72, 520, 1557},
{VGA_FMT_640x480_75, 500, 1495},
{VGA_FMT_640x480_85, 509, 1319},
{VGA_FMT_800x600_56, 625, 2002},
{VGA_FMT_800x600_60, 628, 1868},
{VGA_FMT_800x600_72, 666, 1557},
{VGA_FMT_800x600_75, 625, 1495},
{VGA_FMT_800x600_85, 631, 1319},
{VGA_FMT_1024x768_43, 817, 2607},
{VGA_FMT_1024x768_60, 806, 1868},
{VGA_FMT_1024x768_70, 806, 1601},
{VGA_FMT_1024x768_75, 800, 1495},
{VGA_FMT_1024x768_85, 808, 1319},
{VGA_FMT_1280x720_50, 750, 2238},
{VGA_FMT_1280x720_60, 750, 1868},
//{VGA_FMT_1280x768_60, 798, 1868},
{VGA_FMT_1280x800_60, 830, 1868},
{VGA_FMT_1280x960_60, 1000,1868},
{VGA_FMT_1280x1024_60, 1066, 1868},
{VGA_FMT_1280x1024_75, 1066, 1495},
{VGA_FMT_1366x768_60, 795, 1868},
{VGA_FMT_1400x1050_60RB, 1080, 1868},
{VGA_FMT_1440x900_60, 934, 1868},
{VGA_FMT_1600x1200_60, 1250, 1868},
{VGA_FMT_1920x1080_50, 1125, 2238},
{VGA_FMT_1920x1080_60, 1125, 1868},
{VGA_FMT_1920x1200_60RB, 1245, 1868},
{0xff, 0xffff, 0xffff},
};
MODEDETECTTB adv7441_HDMI_mode[]=
{
{HDMI_YUV_720_480_I60, LCF_480I, FCL_480I },
{HDMI_YUV_720_576_I50, LCF_576I, FCL_576I},
{HDMI_YUV_720_480_P60, LCF_480P, FCL_480P},
{HDMI_YUV_720_576_P50, LCF_576P, FCL_576P},
{HDMI_YUV_1280_720P60, LCF_720P60, FCL_720P60},
{HDMI_YUV_1280_720P50, LCF_720P50, FCL_720P50},
{HDMI_YUV_1920_1080_I60, LCF_1080I60, FCL_1080I60},
{HDMI_YUV_1920_1080_I50, LCF_1080I50, FCL_1080I50},
{HDMI_YUV_1920_1080_P60, LCF_1080P60, FCL_1080P60},
{HDMI_YUV_1920_1080_P50, LCF_1080P50, FCL_1080P50},
{HDMI_YUV_1920_1080_P30, LCF_1080P30, FCL_1080P30},
{HDMI_YUV_1920_1080_P25, LCF_1080P25, FCL_1080P25},
{HDMI_YUV_1920_1080_P24, LCF_1080P24, FCL_1080P24},
{HDMI_RGB_800x600_60, 628, 1868},
{HDMI_RGB_1024x768_60, 806, 1868},
{HDMI_RGB_1280x720_60, 750, 1868},
//{VGA_FMT_1280x768_60, 798, 1868},
{HDMI_RGB_1280x1024_60, 1066, 1868},
{HDMI_RGB_1366x768_60, 795, 1868},
{HDMI_RGB_1400x1050_60, 1080, 1868},
{HDMI_RGB_1440x900_60, 934, 1868},
{HDMI_RGB_1600x1200_60, 1250, 1868},
{HDMI_RGB_1920x1080_60, 1125, 1868},
{HDMI_RGB_1920x1200_60RB, 1245, 1868},
{HDMI_RGB_1280x1024_60, 1199, 2238}, // for case 1280*1024@50 SN:08070111800050132 BL:0xee1; LCF:0x2af; FCL:0x8bc
{0xff, 0xffff, 0xffff},
};
int ADV7441_read(unsigned char MAP_ADDR,unsigned char sub_add)
{
int value;
value = gpio_i2c0_read(MAP_ADDR,sub_add);
return value;
}
void ADV7441_write(unsigned char MAP_ADDR,unsigned char sub_add,unsigned char data_para)
{
gpio_i2c0_write(MAP_ADDR,sub_add,data_para);
return;
}
void Adv7441_Set_YpbprFmt(VIDIN_FMT_E videomode, ADV7441_VIDEO_CHN_E ch)
{
unsigned char i;
unsigned char i2c_addr;
REGTABLE *reglink;
i2c_addr= (ch == ADV7441_VIDEO_CHN_0) ? 0x42:0x40;
CLAER_I2C_ERROR(i2c_addr); //2014-5-9 for correct i2c error
switch(videomode)
{
case YPBPR_FMT_720_576_I50:
reglink = adi7441_YPbPr576i_data;
break;
case YPBPR_FMT_720_480_P60:
reglink = adi7441_YPbPr480p_data;
break;
case YPBPR_FMT_720_576_P50:
reglink = adi7441_YPbPr576p_data;
break;
case YPBPR_FMT_1280_720P60:
reglink = adi7441_YPbPr720p60_data;
break;
case YPBPR_FMT_1280_720P50:
reglink = adi7441_YPbPr720p50_data;
break;
#if 0
case YPBPR_FMT_1280_720P30:
reglink = adi7441_YPbPr720p30_data;
break;
case YPBPR_FMT_1280_720P25:
reglink = adi7441_YPbPr720p25_data;
break;
case YPBPR_FMT_1280_720P24:
reglink = adi7441_YPbPr720p24_data;
break;
#endif
case YPBPR_FMT_1920_1080_I60:
reglink = adi7441_YPbPr1080i60_data;
break;
case YPBPR_FMT_1920_1080_I50:
reglink = adi7441_YPbPr1080i50_data;
break;
case YPBPR_FMT_1920_1080_P60:
reglink = adi7441_YPbPr1080p60_data;
break;
case YPBPR_FMT_1920_1080_P50:
reglink = adi7441_YPbPr1080p50_data;
break;
case YPBPR_FMT_1920_1080_P30:
reglink = adi7441_YPbPr1080p30_data;
break;
case YPBPR_FMT_1920_1080_P25:
reglink = adi7441_YPbPr1080p25_data;
break;
case YPBPR_FMT_1920_1080_P24:
reglink = adi7441_YPbPr1080p24_data;
break;
default:
printk("@@@ADV7441 ch (%d), set unsupport fmt(%d)\n",ch, videomode);
break;
}
i = 0;
while(0xff != reglink[i].ucAddr || 0xff !=reglink[i].ucValue)
{
ADV7441_write(i2c_addr, reglink[i].ucAddr, reglink[i].ucValue);
i++;
}
return;
}
void Adc7441_Set_VgaFmt(VIDIN_FMT_E VidFmt, ADV7441_VIDEO_CHN_E ch)
{
unsigned char i;
unsigned char i2c_addr;
REGTABLE *reglink;
i2c_addr= (ch == ADV7441_VIDEO_CHN_0) ? 0x42:0x40;
CLAER_I2C_ERROR(i2c_addr); //2014-5-9 for correct i2c error
switch(VidFmt)
{
case VGA_FMT_640x480_60:
reglink = adi7441_VGA640x480p60_data;
break;
case VGA_FMT_640x480_72:
reglink = adi7441_VGA640x480p72_data;
break;
case VGA_FMT_640x480_75:
reglink = adi7441_VGA640x480p75_data;
break;
case VGA_FMT_640x480_85:
reglink = adi7441_VGA640x480p85_data;
b
