SST_49LF020.pdf.zip_49lf020_BIOS_datasheet_flash

共1个文件

pdf：1个

版权申诉

bios

datasheet

flash

189 浏览量 2022-09-24 21:42:43 上传评论收藏 362KB ZIP 举报

资源推荐

资源详情

资源评论

收起资源包目录

SST_49LF020.pdf.zip （1个子文件）

SST_49LF020.pdf 449KB

S71175-02-000 5/01 526

The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.

MPF is a trademark of Silicon Storage Technology, Inc. Intel is a registered trademark of Intel Corporation.

These specifications are subject to change without notice.

Advance Information

FEATURES:

• Standard LPC Interface

– Conforms to Intel LPC Interface Specification 1.0

• Organized as 256K x8

• Flexible Erase Capability

– Uniform 4 KByte sectors

– Uniform 16 KByte overlay blocks

– 16 KBytes Top boot block protection

– Chip-Erase for PP Mode

• Single 3.0-3.6V Read and Write Operations

• Superior Reliability

– Endurance: 100,000 Cycles (typical)

– Greater than 100 years Data Retention

• Low Power Consumption

– Active Read Current: 10 mA (typical)

– Standby Current: 10 µA (typical)

• Fast Sector-Erase/Byte-Program Operation

– Sector-Erase Time: 18 ms (typical)

– Block-Erase Time: 18 ms (typical)

– Chip-Erase Time: 70 ms (typical)

– Byte-Program Time: 14 µs (typical)

– Chip Rewrite Time: 4 seconds (typical)

– Single-pulse Program or Erase

– Internal timing generation

• Two Operational Modes

– Low Pin Count (LPC) Interface mode for

in-system operation

– Parallel Programming (PP) Mode for fast production

programming

• LPC Interface Mode

– 5-signal communication interface supporting

byte Read and Write

– 33 MHz clock frequency operation

– WP# and TBL# pins provide hardware write protect

for entire chip and/or top boot block

– Standard SDP Command Set

– Data# Polling and Toggle Bit for

End-of-Write detection

– 5 GPI pins for system design flexibility

• Parallel Programming (PP) Mode

– 11 pin multiplexed address and

8 pin data I/O interface

– Supports fast In-System or PROM programming

for manufacturing

• CMOS I/O Compatibility

• Packages Available

– 32-lead PLCC

– 32-lead TSOP (8mm x 14mm)

PRODUCT DESCRIPTION

The SST49LF020 flash memory device is designed to

interface with the LPC bus for PC and Internet Applicance

applications. It provides protection for the storage and

update of code and data in addition to adding system

design flexibility through five General Purpose Inputs (GPI).

The SST49LF020 is in compliance with Intel Low Pin

Count (LPC) Interface Specification 1.0. Two interface

modes are supported: LPC Mode for In-System program-

ming and Parallel Programming (PP) Mode for fast factory

programming.

The SST49LF020 flash memory device is manufactured

with SST’s proprietary, high performance SuperFlash

Technology. The split-gate cell design and thick oxide

tunneling injector attain better reliability and manufactura-

bility compared with alternate approaches. The

SST49LF020 device significantly improves performance

and reliability, while lowering power consumption. The

SST49LF020 device writes (Program or Erase) with a

single 3.0-3.6V power supply. It uses less energy during

Erase and Program than alternative flash memory tech-

nologies. The total energy consumed is a function of the

applied voltage, current and time of application. Since for

any give voltage range, the SuperFlash technology uses

less current to program and has a shorter erase time, the

total energy consumed during any Erase or Program

operation is less than alternative flash memory technolo-

gies. The SST49LF020 product provides a maximum

Byte-Program time of 20µsec. The entire memory can be

erased and programmed byte-by-byte typically in 4 sec-

onds, when using status detection features such as Tog-

gle Bit or Data# Polling to indicate the completion of

Program operation. The SuperFlash technology provides

fixed Erase and Program time, independent of the num-

ber of Erase/Program cycles that have performed. There-

fore the system software or hardware does not have to

be calibrated or correlated to the cumulative number of

Erase/Program cycles as is necessary with alternative

flash memory technologies, whose Erase and Program

time increase with accumulated Erase/Program cycles.

To protect against inadvertent write, the SST49LF020

device has on-chip hardware and software data (SDP)

protection schemes. It is offered with a typical endurance

of 100,000 cycles. Data retention is rated at greater than

100 years.

2 Megabit LPC Flash

SST49LF020

SST49LF0202 Mb LPC Flash

Advance Information

2 Megabit LPC Flash

SST49LF020

To meet high density, surface mount requirements, the

SST49LF020 device is offered in 32-lead TSOP and 32-

lead PLCC packages. See Figures 1 and 2 for pinouts and

Table 2 for pin descriptions.

Mode Selection and Description

The SST49LF020 flash memory device operates in two

distinct interface modes: the LPC mode and the Parallel

Programming (PP) mode. The Mode pin is used to set the

interface mode selection. If the Mode pin is set to logic

High, the device is in PP mode; while if the Mode pin is set

Low, the device is in the LPC mode. The Mode selection

pin must be configured prior to device operation.

In LPC mode, the device is configured to its host using

standard LPC interface protocol. Communication

between Host and the SST49LF020 occurs via the 4-bit

I/O communication signals, LAD [3:0] and LFRAME#.

In PP mode, the device is programmed via an 11-bit

address and an 8-bit data I/O parallel signals. The address

inputs are multiplexed in row and column selected by con-

trol signal R/C# pin. The row addresses are mapped to the

higher internal addresses, and the column addresses are

mapped to the lower internal addresses. See Device Mem-

ory Map for address assignments.

LPC MODE

Device Operation

The LPC mode uses a 5-signal communication interface, a

4-bit address/data bus, LAD[3:0], and a control line,

LFRAME#, to control operations of the SST49LF020.

Cycle type operations such as Memory Read and Memory

Write are defined in Intel Low Pin Count Interface Specifi-

cation, Revision 1.0. JEDEC Standard SDP (Software

Data Protection) Program and Erase commands

sequences are incorporated into the standard LPC mem-

ory cycles. See Figure 8 through Figure 13 timing diagrams

for command sequences.

LPC operations are transmitted via the 4-bit Address/Data

bus (LAD[3:0]), and follow a particular sequence, depend-

ing on whether they are Read or Write operations. The

standard LPC memory cycle is defined in Table 13.

Both LPC Read and Write operations start in a similar way

as shown in Figures 6 and 7 timing diagrams. The host

(which is the term used here to describe the device driving

the memory) asserts LFRAME# for one or more clocks

and drives a start value on the LAD[3:0] bus.

At the beginning of an operation, the host may hold the

LFRAME# active for several clock cycles, and even change

the Start value. The LAD[3:0] bus is latched every rising

edge of the clock. On the cycle in which LFRAME# goes

inactive, the last latched value is taken as the Start value.

CE# must be asserted one cycle before the start cycle to

select the SST49LF020 for Read and Write operations.

Once the SST49LF020 identifies the operation as valid (a

start value of all zeros), it next expects a nibble that indicates

whether this is a memory read or program cycle. Once this

is received, the device is now ready for the Address and

Data cycles. For Program operation the Data cycle will fol-

low the Address cycle, and for Read operation TAR and

SYNC cycles occur between the Address and Data cycles.

At the end of every operation, the control of the bus must be

returned to the host by a 2 clock TAR cycle.

Device Memory Hardware Write Protection

The Top Boot Lock (TBL#) and Write Protect (WP#) pins

are provided for hardware write protection of device

memory in the SST49LF020. The TBL# pin is used to

write protect four boot sectors (16 KBytes) at the highest

memory address range. WP# pin write protects the

remaining sectors in the flash memory.

An active low signal at the TBL# pin prevents Program and

Erase operations of the top boot sectors. When TBL# pin is

held high, the write protection of the top boot sectors is dis-

abled. The WP# pin serves the same function for the

remaining sectors of the device memory. The TBL# and

WP# pins write protection functions operate independently

of one another.

Both TBL# and WP# pins must be set to their required

protection states prior to starting a Program or Erase

operation. A logic level change occurring at the TBL# or

WP# pin during a Program or Erase operation could

cause unpredictable results.

Reset

A V

on INIT# or RST# pins initiates a device reset. INIT#

and RST# pins have same function internally. It is required

to drive INIT# or RST# pins low during a system reset to

ensure proper CPU initialization.

During a Read operation, driving INIT# or RST# pins low

deselects the device and places the output drivers,

LAD[3:0], in a high-impedance state. The reset signal must

be held low for a minimal duration of time T

RSTP.

A reset

latency will occur if a reset procedure is performed during a

Program or Erase operation. See Table 12, Reset Timing

Parameters, for more information. A device reset during an

active Program or Erase will abort the operation and mem-

Advance Information

2 Megabit LPC Flash

SST49LF020

ory contents may become invalid due to data being altered

had been disrupted from an incomplete Erase or Program

operation.

Registers

There is one register available on the SST49LF020. The

General Purpose Inputs Register. This register appears

at its respective address location in the 4 GByte system

memory map.

General Purpose Inputs Register

The GPI_REG (General Purpose Inputs Register)

passes the state of GPI[4:0] pins at power-up on the

SST49LF020. It is recommended that the GPI[4:0] pins

be in the desired state before LFRAME# is brought low

for the beginning of the next bus cycle, and remain in that

state until the end of the cycle. There is no default value

since this is a pass-through register. The GPI register

appears at FFBC0100H in the 4 GBytes system memory

map. See General Purpose Inputs Register table for the

GPI_REG bits and function.

CE#

The CE# pin, enables and disables the SST49LF020, con-

trolling read and write access of the device. To enable the

SST49LF020, the CE# pin must be driven low one cycle

prior to LFRAME# being driven low. For write (erase or pro-

gram) cycles, the CE# pin must remain low during the inter-

nal programming. When CE# is high, the SST49LF020 is

placed in low-power standby-mode.

LFRAME#

The LFRAME# signifies the start of a frame or the termina-

tion of a broken frame. Asserting LFRAME# for one or

more clock cycle and driving a valid START value on

LAD[3:0] will initiate device operation. The device enters

standby mode when LFRAME# and CE# are high and no

internal operations is in progress.

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles dur-

ing a LPC cycle, the cycle will be terminated and the device

will wait for the ABORT command. The host must drive the

LAD[3:0] with ‘1111b’ (ABORT command) to return the

device to the ready mode. If abort occurs during the inter-

nal write cycle, the data may be incorrectly programmed or

erased. It is required to wait for the Write operation to com-

plete prior to initiation of the abort command. It is recom-

mended to check the write status with Data# Polling (DQ

)

or Toggle Bit (DQ

) pins. One other option is to wait for the

fixed write time to expire.

ENERAL PURPOSE INPUTS REGISTER

Bit Function

Pin#

32-PLCC 32-TSOP

7:5 Reserved - -

4 GPI[4]

Reads status of

general purpose input pin

30 7

3 GPI[3]

Reads status of

general purpose input pin

2 GPI[2]

Reads status of

general purpose input pin

416

1 GPI[1]

Reads status of

general purpose input pin

517

0 GPI[0]

Reads status of

general purpose input pin

618

Advance Information

2 Megabit LPC Flash

SST49LF020

PARALLEL PROGRAMMING MODE

Device Operation

Commands are used to initiate the memory operation func-

tions of the device. The data portion of the software com-

mand sequence is latched on the rising edge of WE#.

During the software command sequence the row address

is latched on the falling edge of R/C# and the column

address is latched on the rising edge of R/C#.

Read

The Read operation of the SST49LF020 device is con-

trolled by OE#. OE# is the output control and is used to

gate data from the output pins. Refer to the Read cycle

timing diagram, Figure 15, for further details.

Reset

Driving the RST# low will initiate a hardware reset of the

SST49LF020.

Byte-Program Operation

The SST49LF020 device is programmed on a byte-by-byte

basis. The Byte-Program operation is initiated by executing

a four-byte-command load sequence for Software Data Pro-

tection with address (BA) and data in the last byte

sequence. During the Byte-Program operation, the row

address (A

-A

) is latched on the falling edge of R/C# and

the column address (A

-A

) is latched on the rising edge

of R/C#. The data bus is latched on the rising edge of WE#.

The Program operation, once initiated, will be completed,

within 20 µs. See Figures 7 and 19 for Program operation

timing diagram and Figure 31 for its flowchart. During the

Program operation, the only valid reads are Data# Polling

and Toggle Bit. During the internal Program operation, the

host is free to perform additional tasks. Any commands writ-

ten during the internal Program operation will be ignored.

Sector-Erase Operation

The Sector-Erase operation allows the system to erase

the device on a sector-by-sector basis. The sector archi-

tecture is based on uniform sector size of 4 KByte. The

Sector-Erase operation is initiated by executing a six-byte-

command load sequence for Software Data Protection

with Sector-Erase command (30H) and sector address

(SA) in the last bus cycle. The internal Erase operation

begins after the sixth WE# pulse. The End-of-Erase can

be determined using either Data# Polling or Toggle Bit

methods. See Figure 20 for Sector-Erase timing wave-

forms. Any commands written during the Sector-Erase

operation will be ignored.

Block-Erase Operation

The Block-Erase Operation allows the system to erase the

device in 16 KByte uniform block size. The Block-Erase

operation is initiated by executing a six-byte-command

load sequence for Software Data Protection with Block-

Erase command (50H) and block address. The internal

Block-Erase operation begins after the sixth WE# pulse.

The End-of-Erase can be determined using either Data#

Polling or Toggle Bit methods. See Figure 21 for Block-

Erase timing waveforms. Any commands written during

the Block-Erase operation will be ignored.

Chip-Erase

The SST49LF020 device provides a Chip-Erase operation

only in PP Mode, which allows the user to erase the entire

memory array to the “1” state. This is useful when the entire

device must be quickly erased.

The Chip-Erase operation is initiated by executing a six-

byte Software Data Protection command sequence with

Chip-Erase command (10H) with address 5555H in the last

byte sequence. The internal Erase operation begins with

the rising edge of the sixth WE#. During the internal Erase

operation, the only valid read is Toggle Bit or Data# Polling.

See Table 4 for the command sequence, Figure 22 for

Chip-Erase timing diagram, and Figure 34 for the flowchart.

Any commands written during the Chip-Erase operation

will be ignored.

Write Operation Status Detection

The SST49LF020 device provides two software means

to detect the completion of a Write (Program or Erase)

cycle, in order to optimize the system write cycle time.

The software detection includes two status bits: Data#

Polling (DQ

) and Toggle Bit (DQ

. The End-of-Write

detection mode is enabled after the rising edge of WE#

which initiates the internal Program or Erase operation.

The actual completion of the nonvolatile write is asyn-

chronous with the system; therefore, either a Data# Poll-

ing or Toggle Bit read may be simultaneous with the

completion of the Write cycle. If this occurs, the system

may possibly get an erroneous result, i.e., valid data may

appear to conflict with either DQ

or DQ

. In order to pre-

vent spurious rejection, if an erroneous result occurs, the

software routine should include a loop to read the

accessed location an additional two (2) times. If both

reads are valid, then the device has completed the Write

cycle, otherwise the rejection is valid.

Advance Information

2 Megabit LPC Flash

SST49LF020

Data# Polling (DQ

)

When the SST49LF020 device is in the internal Program

operation, any attempt to read DQ

will produce the com-

plement of the true data. Once the Program operation is

completed, DQ

will produce true data. The device is then

ready for the next operation. During internal Erase opera-

tion, any attempt to read DQ

will produce a ‘0’. Once the

internal Erase operation is completed, DQ

will produce a

‘1’. The Data# Polling is valid after the rising edge of fourth

WE# pulse for Program operation. For Sector-, Block- or

Chip-Erase, the Data# Polling is valid after the rising edge

of sixth WE# pulse. See Figures 9 and 17 for Data# Polling

timing diagram and Figure 33 for a flowchart.

Toggle Bit (DQ

)

During the internal Program or Erase operation, any con-

secutive attempts to read DQ

will produce alternating “0”

and “1”, i.e., toggling between “0” and “1”. When the inter-

nal Program or Erase operation is completed, the toggling

will stop. The device is then ready for the next operation.

The Toggle Bit is valid after the rising edge of fourth WE#

pulse for Program operation. For Sector-, Block- or Chip-

Erase, the Toggle Bit is valid after the rising edge of sixth

WE# pulse. See Figures 10 and 18 for Toggle Bit timing

diagram and Figure 32 for a flowchart.

Data Protection

The SST49LF020 device provides both hardware and soft-

ware features to protect nonvolatile data from inadvertent

writes.

Hardware Data Protection

Noise/Glitch Protection: A WE# pulse of less than 5 ns will

not initiate a Write cycle.

Power Up/Down Detection: The Write operation is

inhibited when V

is less than 1.5V.

Write Inhibit Mode:

Forcing OE# low, WE# high will inhibit

the Write operation. This prevents inadvertent writes during

power-up or power-down.

Software Data Protection (SDP)

The SST49LF020 provides the JEDEC approved Soft-

ware Data Protection scheme for all data alteration opera-

tion, i.e., Program and Erase. Any Program operation

requires the inclusion of a series of three byte sequence.

The three byte-load sequence is used to initiate the Pro-

gram operation, providing optimal protection from inadvert-

ent Write operations, e.g., during the system power-up or

power-down. Any Erase operation requires the inclusion of

six byte load sequence. The SST49LF020 device is

shipped with the Software Data Protection permanently

enabled. See Table 4 for the specific software command

codes. During SDP command sequence, invalid com-

mands will abort the device to read mode, within T

Electrical Specifications

The AC and DC specifications for the LPC interface signals

(LAD[3:0], LCLCK. LFRAME# and RST#) as defined in

Section 4.2.2 of the “PCI Local Bus specification, Rev. 2.1”.

Refer to Table 5 for the DC voltage and current specifica-

tions. Refer to Tables 11, 12, 14, and 15 for the AC timing

specifications for Clock, Read, Program, Erase and Reset

operations.

Product Identification Mode

The product identification mode identifies the device as

SST49LF020 and the manufacturer as SST.

Design Considerations

SST recommends a high frequency 0.1 µF ceramic capac-

itor to be placed as close as possible between V

and

less than 1 cm away from the V

pin of the device.

Additionally, a low frequency 4.7 µF electrolytic capacitor

from V

to V

should be placed within 5 cm of the V

pin. If you use a socket for programming purposes add an

additional 1-10 µF next to each socket.

The RST# pin must remain stable at V

for the entire dura-

tion of an Erase operation. WP# must remain stable at V

for the entire duration of the Erase and Program operations

for non-boot block sectors. To write data to the top boot

block sectors, the TBL# pin must also remain stable at V

for the entire duration of the Erase and Program operations.

TABLE 1: P

RODUCT IDENTIFICATION

Address Data

Manufacturer’s ID 00000H BFH

Device ID

SST49LF020

00001H 61H

T1.4 526

评论收藏

内容反馈

版权申诉

weixin_42653672

粉丝: 93
资源: 1万+

SST_49LF020.pdf.zip_49lf020_BIOS_datasheet_flash_sst

最新资源

SST_49LF020.pdf.zip_49lf020_BIOS_datasheet_flash_sst

涉税通软件\setup_sst_2012.zip

SSTFlashFlex51 Rev 6.0_MCU下载工具.zip

test - 副本.zip_NC_SST 分布图_sst_sst 图_sst.mnmean.nc文件

intel_sst_603.9600.1948.53972_w8132_www.w5397_adobe_

SST_Flash.rar_ nor flash_flash SST_flash 烧写_nor flash_sst flas

Multivariate_SST_code_MSST_同步挤压_sst_多通道同步挤压_

bpcca-SST-PR_ncl_BPCCA_源码.zip

CJ_Flash_Data-4.zip_cj_flash stm32_sst25vf stm32_stm32 flash

SST结构仿真工具包并行离散事件核心和服务___下载.zip

SST_SST25VF016B.rar_SST25VF016B_pic flash_pic单片机flash_sst25vf pi

STM32_SPI1_2__Flash_SST25VF016B.zip

1_SST39LF200A(1).PDF

SST测试程序.rar_site:www.pudn.com_sst_sst89 _w78e065a_串口 是否

solver_direct_turbulent.rar_CFD_SST湍流模型_kw sst_湍流_湍流计算

A20160012016031.L3m_MO_NSST_sst_4km.nc

EOF_EOFMatlab_；SST_EOF分析_eof_经验正交函数_源码.zip

sst-mfld-platform.rar_platform

SST39VF1601.rar_RD_NORFLASH.r_SST39VF PU_SST39VF160_nor flash_文件

SST_Y.zip_SST 变换_SST_Y_sst时频分析_同步变换_时频同步压缩

冰河的渗透实战笔记-冰河.pdf

大灰狼远控2021最新版，解压密码222

J-LINK V10 V11固件.rar

ISO21434.pdf

Web安全漏洞扫描工具-AWVS14

stm32f103 adc采样+dma传输+fft处理 频率计_fft处理_stm32_ADCFFT_频率计_ADC采样_

CTF 竞赛入门指南（ctf-all-in-one）.pdf

Web中间件常见漏洞总结.pdf

jts-1.14.zip

CobaltStrike4.4.zip

最新资源

SST测试程序.rar_site:www.pudn.com_sst_sst89 _w78e065a_串口是否

stm32f103 adc采样+dma传输+fft处理频率计_fft处理_stm32_ADCFFT_频率计_ADC采样_