pwm.rar_pwm_pwm vhdl_verlog_verlog PWM_基于VHDL_PWM

PWMusermanual

Author:ZhuXu

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Features

• WorkasonePWMoronetimer.

• 16bitsmaincounter.

• PWM/TimercanchoosebetweenWishboneinterfaceclockorexternalclockas

fr

equency.

)12/(1

16



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AlloperationsofthisPWMcoreiscontrolledbymanipulatingregistersinsidethe

Bothperiodanddutycyclearedefinedbynumberofclockcycles. When main

counterenablebitisresetthemaincounterwillstoprunningando_pwmwillstop

changinguntilthemaincounterenablebitissetagainorthecounterlogicisreset

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Whenthenumberstoresinmaincounterreachesorexceedsthenumberstoredin

register period an interrupt is generated and output through o_pwm. Then the

Clockforincrementingthemaincountercanbedownclockedbefore entering

maincounterlogic.Frequencycanbedividedbyoddorevennumber.Divisoris

storedin16-bitregister.Ifdivisorequals0or1,nodownclockingisperformed.Else,

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Maincounterreset

Maincountercanberesetbysystemresetorbysettingctrlbit7.Whenchanging

fromPWMmodetotimermodemaincountermustberesetbeforetimerstarts.

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Interrupt

Name Address Width Access Description

Ctrl Base+0 8 R/W Core′soperationcontrolregister

Divisor Base+2 16 R/W Storesdivisorfordownclocking.

Period Base+4 16 R/W

DC Base+6 16 R/W

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